W48S87-72 Datasheet, PDF (14/19 Pages) Cypress Semiconductor – Desktop/Notebook Frequency Generator

W48S87-72
AC Electrical Characteristics
T_A = 0°C to +70°C, V_DD = V_DDQ3 = 3.3V±5% (3.135–3.465V) f_XTL = 14.31818 MHz, V_DDQ2 = 2.5±5%
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
CPU = 66.8 MHz CPU = 60 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.5V
15
16.7
ns
f
Frequency, Actual
Determined by PLL divider ratio
66.8
59.876
MH
z
t_H
High Time
Duration of clock cycle above 2.4V
5.2
6
ns
t_L
Low Time
Duration of clock cycle below 0.4V
5
5.8
ns
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
1
41
4 V/ns
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
1
41
4 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45 52 55 45 52 55 %
1.25V
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V.
250
250 ps
Maximum difference of cycle time be-
tween two adjacent cycles.
t_SK
Output Skew
Measured on rising edge at 1.25V
250
250 ps
f_ST
Frequency Stabilization Assumes full supply voltage reached
3
from Power-up (cold within 1 ms from power-up. Short cy-
start)
cles exist prior to frequency stabiliza-
tion.
3 ms
Z_o
AC Output Impedance Average value during switching transi-
10
tion. Used for determining series ter-
mination value.
10
Ω
SDRAM Clock Outputs, SDRAM0:7 (Lump Capacitance Test Load = 30 pF)
CPU = 66.8 MHz CPU = 60 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.5V
15
16.7
ns
f
Frequency, Actual
Determined by PLL divider ratio
66.8
59.876
MHz
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
1
41
4 V/ns
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
1
41
4 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45 50 55 45 50 55 %
1.5V
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Max-
250
imum difference of cycle time between
two adjacent cycles.
250 ps
t_SK
Output Skew
Measured on rising edge at 1.5V
100
100
ps
t_SK
CPU to SDRAM Clock Covers all CPU/SDRAM outputs. Mea-
500
Skew
sured on rising edge at 1.5V.
500 ps
f_ST
Frequency Stabiliza- Assumes full supply voltage reached
3
tion from Power-up
within 1 ms from power-up. Short cycles
(cold start)
exist prior to frequency stabilization.
3 ms
Z_o
AC Output Impedance Average value during switching transi-
16
tion. Used for determining series termi-
nation value.
16
Ω
14