W48S87-72 Datasheet, PDF (15/19 Pages) Cypress Semiconductor – Desktop/Notebook Frequency Generator

W48S87-72
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF)
CPU = 66.8 MHz CPU = 60 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.5V
30
33.3
ns
f
Frequency, Actual
Determined by PLL divider ratio
33.4
29.938
MHz
t_H
High Time
Duration of clock cycle above 2.4V
12
13.3
ns
t_L
Low Time
Duration of clock cycle below 0.4V
12
13.3
ns
t_R
Output Rise Edge Rate
1
41
4 V/ns
t_F
Output Fall Edge Rate
1
41
4 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45 51 55 45 51 55 %
1.5V
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maxi-
250
mum difference of cycle time between
two adjacent cycles.
250 ps
t_SK
Output Skew
Measured on rising edge at 1.5V
t_O
CPU to PCI Clock
Covers all CPU/PCI outputs. Measured 1
Skew
on rising edge at 1.5V. CPU leads PCI
output.
250
41
250 ps
4 ns
f_ST
Frequency Stabiliza- Assumes full supply voltage reached
3
tion from Power-up within 1 ms from power-up. Short cycles
(cold start)
exist prior to frequency stabilization.
3 ms
Z_o
AC Output Impedance Average value during switching transi-
30
tion. Used for determining series termi-
nation value.
30
Ω
I/O APIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
f
t_R
t_F
t_D
f_ST
Z_o
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization
from Power-up (cold start)
AC Output Impedance
Test Condition/Comments
Frequency generated by crystal oscillator
Measured on rising and falling edge at 1.25V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition.
Used for determining series termination value.
CPU = 60/66.8 MHz
Min. Typ. Max.
14.31818
1
4
1
4
45 52.5 55
1.5
15
Unit
MHz
V/ns
V/ns
%
ms
Ω
15