W48S87-72 Datasheet, PDF (5/19 Pages) Cypress Semiconductor – Desktop/Notebook Frequency Generator

W48S87-72
Serial Data Interface
The W48S87-72 features a two-pin, serial data interface that
can be used to configure internal register settings that control
particular device functions. Upon power-up, the W48S87-72
initializes with default register settings, therefore the use of this
serial data interface is optional. The serial interface is write-
only (to the clock chip) and is the dedicated function of device
pins SDATA and SCLOCK. In motherboard applications,
SDATA and SCLOCK are typically driven by two logic outputs
of the chipset. Clock device register changes are normally
made upon system initialization, if any are required. The inter-
face can also be used during system operation for power man-
agement functions. Table 2 summarizes the control functions
of the serial data interface.
Operation
Data is written to the W48S87-72 in ten bytes of eight bits
each. Bytes are written in the order shown in Table 3.
Table 2. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis-
abled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock out-
puts to unused SDRAM DIMM socket or PCI
slot.
48-/24-MHz Clock Output 48-/24-MHz clock outputs can be set to 48 MHz or Provides flexibility in Super I/O and USB de-
Frequency Selection
24 MHz.
vice selection.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections beyond the
60- and 66.6-MHz selections that are provided by
the SEL60/66 input pin. Frequency is changed in a
smooth and controlled fashion.
For alternate CPU devices, and power man-
agement options. Smooth frequency transi-
tion allows CPU frequency change under nor-
mal system operation.
Output Three-state
Puts all clock outputs into a high-impedance state. Production PCB testing.
Test Mode
All clock outputs toggle in relation with X1 input,
internal PLL is bypassed. Refer to Table 4.
Production PCB testing.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be writ-
duction device testing.
ten as 0.
Table 3. Byte Writing Sequence
Byte Sequence Byte Name
1
Slave Address
2
Command
Code
3
Byte Count
4
Data Byte 0
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
11
Data Byte 7
Bit Sequence
11010010
Don’t Care
Don’t Care
Refer to Table 4
Byte Description
Commands the W48S87-72 to accept the bits in Data Bytes 0–7 for
internal register configuration. Since other devices may exist on the
same common serial data bus, it is necessary to have a specific slave
address for each potential receiver. The slave receiver address for the
W48S87-72 is 11010010. Register setting will not be made if the Slave
Address is not correct (or is for an alternate slave receiver).
Unused by the W48S87-72, therefore bit values are ignored (don’t care).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
Unused by the W48S87-72, therefore bit values are ignored (don’t care).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Byte Count Byte is part of the standard serial com-
munication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
The data bits in Data Bytes 0–7 set internal W48S87-72 registers that
control device operation. The data bits are only accepted when the Ad-
dress Byte bit sequence is 11010010, as noted above. For description
of bit control functions, refer to Table 4, Data Byte Serial Configuration
Map.
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