W48S87-72 Datasheet, PDF (3/19 Pages) Cypress Semiconductor – Desktop/Notebook Frequency Generator

W48S87-72
Pin Definitions (continued)
Pin
Pin Name
No.
PWR_DWN#
44
MODE
SDATA
SCLOCK
VDDQ3
VDDQ2
GND
6
19
20
7, 15, 21, 25
28, 34, 48
46, 40
3, 10, 17,
24, 31, 37,
43
Pin
Type
I
I
I/O
I
P
P
G
Pin Description
Power-Down Control: When this input is LOW, the device goes into a low-
power standby condition. All outputs are actively held LOW while in power-
down. CPU, SDRAM, and PCI clock outputs are stopped LOW after completing
a full clock cycle (2–4 CPU clock cycle latency). When brought HIGH, CPU,
SDRAM, and PCI outputs start with a full clock cycle at full operating frequency
(3 ms maximum latency).
Mode Control: This input selects the function of device pin 26
(SDRAM7/PCI_STOP#) and pin 27 (SDRAM6/CPU_STOP#). Refer to descrip-
tion for those pins.
Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
Power Connection: Power supply for PCI0:5, REF0:1, and 48/24MHz output
buffers. Connected to 3.3V supply.
Power Connection: Power supply for IOAPIC0, CPU0:3 output buffer. Con-
nected to 2.5V supply.
Ground Connection: Connect all ground pins to the common system ground
plane.
3