W312-02 Datasheet, PDF (6/21 Pages) Cypress Semiconductor – FTG for VIA K7 Series Chipset with Programmable Output Frequency

W312-02
W312-02 Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 0: Control Register 0
2. All unused register bits (reserved and N/A) should be writ-
ten to a “0” level.
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization.
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
–
–
–
–
–
–
–
–
Name
Spread Enable
Spread Select2
Spread Select1
Spread Select0
SEL3
SEL2
SEL1
SEL0
Default
Description
0
0 = Disabled
1 = Enabled
0
‘000’ = ±0.25%
0
‘001’ = –0.5%
‘010’ = ±0.5%
0
‘011’ = ±0.38%
‘100’ = Reserved
‘101’ = Reserved
‘110’ = Reserved
‘111’ = Reserved
0
SW Frequency selection bits. See Table 4.
0
0
0
Byte 1: Control Register 1
Bit
Bit 7
Bit 6
Pin#
42, 41
39, 38
Bit 5
6
Bit 4
7
Bit 3
–
Bit 2
28
Bit 1
27
Bit 0
26
Name
CPUT0, CPUC0
CPUT_CS,
CPUC_CS
48MHz
24_48MHz
Reserved
AGP2
AGP1
AGP0
Default
1
1
(Active/Inactive)
(Active/Inactive)
Description
1
(Active/Inactive)
1
(Active/Inactive)
0
Reserved
1
(Active/Inactive)
1
(Active/Inactive)
1
(Active/Inactive)
Document #: 38-07259 Rev. *B
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