W312-02 Datasheet, PDF (19/21 Pages) Cypress Semiconductor – FTG for VIA K7 Series Chipset with Programmable Output Frequency

W312-02
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
f_D
Deviation from 24 MHz
(24.004 – 24)/24
m/n
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms
from Power-up (cold start) from power-up. Short cycles exist prior to fre-
quency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Min.
0.5
0.5
45
Typ.
24.004
+167
57/34
40
Max.
2
2
55
3
Unit
MHz
ppm
V/ns
V/ns
%
ms
Ω
R8
CPUCLK_T
47
Clock Chip
CPUDriver
R9
CPUCLK_C
47
VDD
+ _V1
3.3
-
Z0 = 52Ω
Length = 5”
T1
Z0 = 52Ω
Length = 5”
T4
1.5V
Z0 = 52Ω
Length = 3”
T2
R1
68
20p
1.5V
Z0 = 52Ω
Length = 3”
T5
R3
68
20p
Figure 1. K7 Open Drain Clock Driver Test Circuit
Document #: 38-07259 Rev. *B
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