W312-02 Datasheet, PDF (17/21 Pages) Cypress Semiconductor – FTG for VIA K7 Series Chipset with Programmable Output Frequency

W312-02
DC Electrical Characteristics: T_A = 0°C to +70°C, V_DD = 3.3V±5% and 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
V_TH
X1 Input Threshold Voltage^[4]
C_LOAD
Load Capacitance, Imposed on
External Crystal^[5]
C_IN,X1
X1 Input Capacitance^[6]
Pin Capacitance/Inductance
V_DD = 3.3V
Pin X2 unconnected
1.65
V
18
pF
TBD
pF
C_IN
C_OUT
L_IN
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
Except X1 and X2
5
pF
6
pF
7
nH
AC Electrical Characteristics
T_A = 0°C to +70°C, V_DDQ3 = 3.3V±5%, f_XTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum is disabled.
CPU Clock Outputs (CPUT0, CPUC0, CPU_CS)^[7]
Parameter
Description
Test Condition/Comments
t_R
Output Rise Edge Rate CPU_CS
t_F
Output Fall Edge Rate CPU_CS
t_D
Duty Cycle
Measured at 50% point
t_JC
Jitter, Cycle to Cycle
f_ST
Frequency Stabilization Assumes full supply voltage reached
from Power-up (cold within 1 ms from power-up. Short
start)
cycles exist prior to frequency
stabilization.
Z_o
AC Output Impedance V_O = V_X
CPU = 100 MHz
Min. Typ. Max.
1.0
4.0
1.0
4.0
45
55
250
3
50
CPU = 133 MHz
Min. Typ. Max. Unit
1.0
4.0 V/ns
1.0
4.0 V/ns
45
55 %
250 ps
3
ms
50
Ω
Notes:
5. The W312-02 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
18 pF; this includes typical stray capacitance of short PCB traces to crystal.
6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
7. Refer to Figure 1 for K7 operation clock driver test circuit.
Document #: 38-07259 Rev. *B
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