CYP15G0101DXB_11 Datasheet, PDF (6/44 Pages) Cypress Semiconductor – Single-channel HOTLink II Transceiver Compliant to multiple standards

CYP15G0101DXB
CYV15G0101DXB
Pin Descriptions
CYP(V)15G0101DXB single-channel HOTLink II
Pin Name I/O Characteristics Signal Description
Transmit Path Data Signals
TXPER
LVTTL output,
changes relative to
REFCLK↑^[3]
Transmit path parity error. Active HIGH. Asserted (HIGH) if parity checking is enabled
(PARCTL ≠ LOW) and a parity error is detected at the encoder. This output is HIGH for one
transmit character-clock period to indicate detection of a parity error in the character
presented to the encoder.
If a parity error is detected, the character in error is replaced with a C0.7 character to force a
corresponding bad-character detection at the remote end of the link. This replacement takes
place regardless of the encoded/un-encoded state of the interface.
When BIST is enabled for the specific transmit channel, BIST progress is presented on this
output. Once every 511 character times (plus a 16-character Word Sync Sequence when the
receive channel is clocked by REFCLK, i.e., RXCKSEL = LOW), the TXPER signal pulses
HIGH for one transmit-character clock period (if RXCKSEL = MID) or seventeen
transmit-character clock periods (if RXCKSEL = LOW or HIGH) to indicate a complete pass
through the BIST sequence. For RXCKSEL = LOW or HIGH, If TXMODE[1:0] = LL, then no
Word Sync Sequence is sent in BIST, and TXPER pulses HIGH for one transmit-character
clock period.
This output also provides an indication of a phase-align buffer underflow/overflow condition.
When the phase-align buffer is enabled (TXCKSEL ≠ LOW, or TXCKSEL = LOW and
TXRATE = HIGH), and an underflow/overflow condition is detected, TXPER is asserted and
remains asserted until either an atomic Word Sync Sequence is transmitted or TXRST is
sampled LOW to recenter the phase-align buffer.
TXCT[1:0]
LVTTL input,
synchronous,
sampled by
TXCLK↑ or
REFCLK↑^[3]
Transmit control. These inputs are captured on the rising edge of the transmit interface clock
as selected by TXCKSEL, and are passed to the encoder or transmit shifter. They identify
how the TXD[7:0] characters are interpreted. When the encoder is enabled, these inputs
determine if the TXD[7:0] character is encoded as data, a special character code, a K28.5 fill
character or a Word Sync Sequence. When the encoder is bypassed, these inputs are
interpreted as data bits. See Table 1 for details.
TXD[7:0]
LVTTL input,
synchronous,
sampled by
TXCLK↑ or
REFCLK↑^[3]
Transmit data inputs. These inputs are captured on the rising edge of the transmit interface
clock as selected by TXCKSEL, and passed to the encoder or transmit shifter.
When the encoder is enabled (TXMODE[1] ≠ LOW), TXD[7:0] specify the specific data or
command character to be sent. When the encoder is bypassed, these inputs are interpreted
as data bits of the 10-bit input character. See Table 1 for details.
TXOP
LVTTL input,
synchronous,
internal pull-up,
sampled by
TXCLK↑ or
REFCLK↑^[3]
Transmit path odd parity. When parity checking is enabled (PARCTL ≠ LOW), the parity
captured at this input is XORed with the data on the TXD bus (and sometimes TXCT[1:0]) to
verify the integrity of the captured character. See Table 2 for details.
SCSEL
LVTTL input,
synchronous,
internal pull-down,
sampled by
TXCLK↑ or
REFCLK↑^[3]
Special character select. Used in some transmit modes along with TXCTx[1:0] to encode
special characters or to initiate a Word Sync Sequence. When the transmit path is configured
to select TXCLK to clock the input register (TXCKSEL = MID or HIGH), SCSEL is captured
relative to TXCLK↑.
Note
3. When REFCLK is configured for half-rate operation (TXRATE = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges of
REFCLK.
Document Number: 38-02031 Rev. *M
Page 6 of 44
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