CYP15G0101DXB_11 Datasheet, PDF (25/44 Pages) Cypress Semiconductor – Single-channel HOTLink II Transceiver Compliant to multiple standards

CYP15G0101DXB
CYV15G0101DXB
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature................................. –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Supply voltage to ground potential ...............–0.5 V to +3.8 V
DC voltage applied to LVTTL outputs
in high Z State...................................... –0.5 V to V_CC + 0.5 V
Output current into LVTTL outputs (LOW) ................... 60 mA
DC input voltage .................................. –0.5 V to V_CC + 0.5 V
Static discharge voltage........................................... > 2000 V
(per MIL-STD-883, method 3015)
Latch-up current ..................................................... > 200 mA
Power-up Requirements
The CYP(V)15G0101DXB requires one power-supply. The
voltage on any input or I/O pin cannot exceed the power pin
during power-up.
Operating Range
Range
Ambient Temperature
Commercial
0 °C to +70 °C
Industrial
–40 °C to +85 °C
V_CC
+3.3 V ± 5%
+3.3 V ± 5%
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min
Max Unit
LVTTL-compatible Outputs
V_OHT
Output HIGH voltage
V_OLT
Output LOW voltage
I_OST
Output short circuit current
I_OZL
High Z output leakage current
LVTTL-compatible Inputs
I_OH = − 4 mA, V_CC = Min
I_OL = 4 mA, V_CC = Min
V_OUT = 0V^[26]
2.4
V_CC
V
0
0.4
V
–20
–100 mA
–20
20
µA
V_IHT
V_ILT
I_IHT
Input HIGH voltage
Input LOW voltage
Input HIGH current
I_ILT
Input LOW current
I_IHPDT
Input HIGH current with internal pull-down
I_ILPUT
Input LOW current with internal pull-up
LVDIFF Inputs: REFCLK±
V_DIFF[27]
Input differential voltage
V_IHHP
Highest input HIGH voltage
V_ILLP
Lowest input LOW voltage
V_COMREF[28] Common mode range
3-Level Inputs
REFCLK Input, V_IN = V_CC
Other Inputs, V_IN = V_CC
REFCLK Input, V_IN = 0.0 V
Other Inputs, V_IN = 0.0 V
V_IN = V_CC
V_IN = 0.0 V
2.0
V_CC + 0.3 V
–0.5
0.8
V
–
1.5
mA
–
+40
µA
–
–1.5
mA
–
-40
µA
–
+200
µA
–
–200
µA
400
V_CC
mV
1.2
V_CC
V
0.0
V_CC / 2
V
1.0
V_CC – 1.2 V
V_IHH
3-level input HIGH voltage
V_IMM
3-level input MID voltage
V_ILL
3-level input LOW voltage
I_IHH
Input HIGH current
I_IMM
Input MID current
I_ILL
Input LOW current
Differential CML Serial Outputs: OUT1±, OUT2±
Min ≤ V_CC ≤ Max
Min ≤ V_CC ≤ Max
Min ≤ V_CC ≤ Max
V_IN = V_CC
V_IN = V_CC/2
V_IN = GND
0.87 × V_CC
V_CC
V
0.47 × V_CC 0.53 × V_CC V
0.0
0.13 × V_CC V
–
200
µA
–50
50
µA
–
–200
µA
V_OHC
Output HIGH voltage
(V_CC referenced)
100 Ω differential load
150 Ω differential load
V_CC – 0.5 V_CC − 0.2 V
V_CC − 0.5 V_CC − 0.2 V
Notes
26. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
27. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the
true (+) input is more positive than the complement (−) input. A logic-0 exists when the complement (−) input is more positive than true (+) input.
28. The common mode range defines the allowable range of REFCLK+ and REFCLK− when REFCLK+ = REFCLK−. This marks the zero-crossing between the true
and complement inputs as the signal switches between a logic-1 and a logic-0.
Document Number: 38-02031 Rev. *M
Page 25 of 44
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