CYP15G0101DXB_11 Datasheet, PDF (21/44 Pages) Cypress Semiconductor – Single-channel HOTLink II Transceiver Compliant to multiple standards

CYP15G0101DXB
CYV15G0101DXB
Following a device reset, it is necessary to enable the transmit
and receive channels for normal operation. This can be done by
sequencing the appropriate values on the BOE[1:0] inputs while
the OELE and RXLE signals are raised and lowered. For
systems that do not require dynamic control of power, or want
the part to power-up in a fixed configuration, it is also possible to
strap the RXLE and OELE control signals HIGH to permanently
enable their associated latches. Connection of the associated
BOE[1:0] signals to a stable HIGH will then enable the transmit
and receive channels as soon as the TRSTZ signal is
deasserted.
Output Bus
The receive channel presents a 12-signal output bus consisting
of
■ an eight-bit data bus
■ a three-bit status bus
■ a parity bit.
The bit assignments of the Data and Status are dependent on the
setting of DECMODE. This mapping is shown in Table 13.
Table 13. Output Register Bit Assignments^[23]
Signal Name
DECMODE = LOW
DECMODE = MID
or HIGH
RXST[2] (LSB)
RXST[1]
COMDET
DOUT[0]
RXST[2]
RXST[1]
RXST[0]
DOUT[1]
RXST[0]
RXD[0]
DOUT[2]
RXD[0]
RXD[1]
DOUT[3]
RXD[1]
RXD[2]
DOUT[4]
RXD[2]
RXD[3]
DOUT[5]
RXD[3]
RXD[4]
DOUT[6]
RXD[4]
RXD[5]
DOUT[7]
RXD[5]
RXD[6]
DOUT[8]
RXD[6]
RXD[7] (MSB)
DOUT[9]
RXD[7]
When the 10B/8B decoder is bypassed (DECMODE = LOW),
the framed 10-bit character is presented to the receiver output
register, along with a status output (COMDET) indicating if the
character in the output register is one of the selected framing
characters. The bit usage and mapping of the external signals to
the raw 10B transmission character is shown in Table 14.
Table 14. Decoder Bypass Mode (DECMODE = LOW)
Signal Name
RXST[2] (LSB)
RXST[1]
RXST[0]
RXD[0]
RXD[1]
RXD[2]
RXD[3]
RXD[4]
RXD[5]
RXD[6]
RXD[7] (MSB)
Bus Weight
COMDET
2⁰
2¹
2²
2³
2⁴
2⁵
2⁶
2⁷
2⁸
2⁹
10B Name
a
b
c
d
e
i
f
g
h
j
The COMDET output is HIGH when the character in the output
register contains the selected framing character at the proper
character boundary, and LOW for all other bit combinations.
When the low-latency framer and half-rate receive port clocking
is also enabled (RFMODE = LOW, RXRATE = HIGH, and
RXCKSEL = MID), the framer will stretch the recovered clock to
the nearest 20-bit boundary such that the rising edge of RXCLK+
occurs when COMDET = HIGH in the output register.
When the Cypress or alternate-mode framer is enabled and
half-rate receive port clocking is also enabled (RFMODE ≠ LOW
and RXRATE = HIGH), the output clock is not modified when
framing is detected, but a single pipeline stage may be added or
subtracted from the data stream by the framer logic such that the
rising edge of RXCLK+ occurs when COMDET = HIGH in the
output register. This adjustment only occurs when the framer is
enabled (RFEN = HIGH). When the framer is disabled, the clock
boundaries are not adjusted, and COMDET may be asserted
during the rising edge of RXCLK– (if an odd number of
characters were received following the initial framing).
Note
23. The RXOP output is also driven from the Output Register, but its interpretation is under the separate control of PARCTL.
Document Number: 38-02031 Rev. *M
Page 21 of 44
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