CYP15G0101DXB_11 Datasheet, PDF (12/44 Pages) Cypress Semiconductor – Single-channel HOTLink II Transceiver Compliant to multiple standards

CYP15G0101DXB
CYV15G0101DXB
CYP(V)15G0101DXB HOTLink II Operation
The CYP(V)15G0101DXB is a highly configurable device
designed to support reliable transfer of large quantities of data
using high-speed serial links from a single source to one or more
destinations.
CYP(V)15G0101DXB Transmit Data Path
Operating Modes
The transmit path of the CYP(V)15G0101DXB supports a single
character-wide data path. This data path is used in multiple
operating modes as controlled by the TXMODE[1:0] inputs.
Input Register
The bits in the input register support different assignments,
based on if the character is unencoded, encoded with two control
bits, or encoded with three control bits. These assignments are
shown in Table 1.
Table 1. Input Register Bit Assignments^[9]
Signal Name
TXD[0] (LSB)
TXD[1]
TXD[2]
TXD[3]
TXD[4]
TXD5]
TXD[6]
TXD[7]
TXCT[0]
TXCT[1] (MSB)
SCSEL
Unencoded
(Encoder
Bypassed)
DIN[0]
DIN[1]
DIN[2]
DIN[3]
DIN[4]
DIN[5]
DIN[6]
DIN[7]
DIN[8]
DIN[9]
N/A
Encoded
(Encoder Enabled)
Two-bit
Control
Three-bit
Control
TXD[0]
TXD[0]
TXD[1]
TXD[1]
TXD[2]
TXD[2]
TXD[3]
TXD[3]
TXD[4]
TXD[4]
TXD[5]
TXD[5]
TXD[6]
TXD[6]
TXD[7]
TXD[7]
TXCT[0] TXCT[0]
TXCT[1] TXCT[1]
N/A
SCSEL
The input register captures a minimum of eight data bits and two
control bits on each input clock cycle. When the encoder is
bypassed, the TXCT[1:0] control bits are part of the pre-encoded
10-bit data character.
When the encoder is enabled (TXMODE[1] ≠ LOW), the
TXCT[1:0] bits are interpreted along with the TXD[7:0] character
to generate the specific 10-bit transmission character. When
TXMODE[0] ≠ HIGH, an additional special character select
(SCSEL) input is also captured and interpreted. This SCSEL
input is used to modify the encoding of the characters.
Phase-Align Buffer
Data from the input register is passed either to the encoder or to
the phase-align buffer. When the transmit path is operated
synchronous to REFCLK↑ (TXCKSEL = LOW and
TXRATE = LOW), the phase-align buffer is bypassed and data is
passed directly to the parity check and encoder block to reduce
latency.
When an input register clock with an uncontrolled phase
relationship to REFCLK is selected (TXCKSEL ≠ LOW) or if data
is captured on both edges of REFCLK (TXRATE = HIGH), the
phase-align buffer is enabled. This buffer is used to absorb clock
phase differences between the presently selected input clock
and the internal character clock.
Initialization of the phase-align buffer takes place when the
TXRST input is sampled LOW by two consecutive rising edges
of REFCLK. When TXRST is returned HIGH, the present input
clock phase relative to REFCLK↑ is set. TXRST is an
asynchronous input, but is sampled internally to synchronize it to
the internal transmit path state machine.
Once set, the input clock is allowed to skew in time up to half a
character period in either direction relative to REFCLK↑; that
is ±180°. This time shift allows the delay path of the character
clock (relative to REFLCK↑) to change due to operating voltage
and temperature, while not affecting the design operation.
If the phase offset, between the initialized location of the input
clock and REFCLK↑, exceeds the skew handling capabilities of
the phase-align buffer, an error is reported on the TXPER output.
This output indicates a continuous error until the phase-align
buffer is reset. While the error remains active, the transmitter
outputs a continuous C0.7 character to indicate to the remote
receiver that an error condition is present in the link.
In specific transmit modes, it is also possible to reset the
phase-align buffer with minimal disruption of the serial data
stream. When the transmit interface is configured for generation
of atomic Word Sync Sequences (TXMODE[1] = MID) and a
phase-align buffer error is present, the transmission of a Word
Sync Sequence will recenter the phase-align buffer and clear the
error condition.^[10]
Parity Support
In addition to the ten data and control bits that are captured at
the transmit input register, a TXOP input is also available. This
allows the CYP(V)15G0101DXB to support ODD parity
checking. Parity checking is available for all operating modes
(including encoder bypass). The specific mode of parity checking
is controlled by the PARCTL input, and operates per Table 2.
When PARCTL = MID (open) and the encoder is enabled
(TXMODE[1] ≠ LOW), only the TXD[7:0] data bits are checked
for ODD parity along with the TXOP bit. When PARCTL = HIGH
with the encoder enabled (or MID with the encoder bypassed),
the TXD[7:0] and TXCT[1:0] inputs are checked for ODD parity
along with the TXOP bit. When PARCTL = LOW, parity checking
is disabled.
Notes
9. The TXOP input is also captured in the input register, but its interpretation is under the separate control of PARCTL.
10. One or more K28.5 characters may be added or lost from the data stream during this reset operation. When used with non-Cypress devices that require a complete
16-character Word Sync Sequence for proper receive elasticity buffer alignment, it is recommend that the sequence be followed by a second Word Sync Sequence
to ensure proper operation.
Document Number: 38-02031 Rev. *M
Page 12 of 44
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