CYP15G0101DXB_11 Datasheet, PDF (1/44 Pages) Cypress Semiconductor – Single-channel HOTLink II Transceiver Compliant to multiple standards

CYP15G0101DXB
CYV15G0101DXB
Single-channel HOTLink II™ Transceiver
Single-channel HOTLink II™ Transceiver
Features
■ Second-generation HOTLink^® technology
■ Compliant to multiple standards
❐ ESCON^®, DVB-ASI, fibre channel and gigabit ethernet
(IEEE802.3z)
❐ CPRI™ compliant
❐ CYV15G0101DXB compliant to SMPTE 259M and SMPTE
292M
❐ 8B/10B encoded or 10-bit unencoded data
■ Single-channel transceiver operates from 195 to 1500 MBaud
serial data rate
■ Selectable parity check/generate
■ Selectable input clocking options
■ Selectable output clocking options
■ MultiFrame™ Receive Framer
❐ Bit and byte alignment
❐ Comma or full K28.5 detect
❐ Single- or multi-byte framer for byte alignment
❐ Low-latency option
■ Synchronous LVTTL parallel input and parallel output interface
■ Internal phase-locked loops (PLLs) with no external PLL
components
■ Dual differential PECL-compatible serial inputs
❐ Internal DC-restoration
■ Dual differential PECL-compatible serial outputs
❐ Source matched for driving 50 Ω transmission lines
❐ No external bias resistors required
❐ Signaling-rate controlled edge-rates
■ Optional elasticity buffer in receive path
■ Optional phase align buffer in transmit path
■ Compatible with
❐ Fiber-optic modules
❐ Copper cables
❐ Circuit board traces
■ JTAG boundary scan
■ Built-in self-test (BIST) for at-speed link testing
■ Per-channel link quality indicator
❐ Analog signal detect
❐ Digital signal detect
■ Low power 1.25 W at 3.3 V typical
■ Single 3.3 V supply
■ 100-ball BGA
■ Pb-free package option available
■ 0.25 µ BiCMOS technology
Functional Description
The CYP15G0101DXB^[1] single-channel HOTLink II™
transceiver is a point-to-point communications building block
allowing the transfer of data over a high-speed serial link (optical
fiber, balanced, and unbalanced copper transmission lines) at
signaling speeds ranging from 195 to 1500 MBaud.
The transmit channel accepts parallel characters in an input
register, encodes each character for transport, and converts it to
serial data. The receive channel accepts serial data and converts
it to parallel data, frames the data to character boundaries,
decodes the framed characters into data and special characters,
and presents these characters to an output register. Figure 1
illustrates typical connections between independent host
systems and corresponding CYP(V)15G0101DXB parts. As a
second-generation HOTLink device, the CYP(V)15G0101DXB
extends the HOTLink II family with enhanced levels of
integration and faster data rates, while maintaining serial-link
compatibility (data, command, and BIST) with other HOTLink
devices.
Figure 1. HOTLink II System Connections
10
10
Serial Link
Backplane or Cabled
Connections
10
10
Note
1. CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE
292M pathological test requirements. CYP(V)15G0101DXB refers both devices.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-02031 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 29, 2011
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