CY8C38 Datasheet, PDF (52/100 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC)

PRELIMINARY
PSoC^®3: CY8C38 Family Data Sheet
8.3 Comparators
The CY8C38 family of devices contains four comparators in a
device. Comparators have these features:
„ Input offset factory trimmed to less than 5 mV
„ Rail-to-rail common mode input range (Vssa to Vdda)
„ Speed and power can be traded off by using one of three
modes: fast, slow, or ultra low power
„ Comparator outputs can be routed to look up tables to perform
simple logic functions and then can also be routed to digital
blocks
„ The positive input of the comparators may be optionally passed
through a low pass filter. Two filters are provided
„ Comparator inputs can be connections to GPIO, DAC outputs
and SC block outputs
8.3.1 Input and Output Interface
The positive and negative inputs to the comparators come from
the analog global buses, the analog mux line, the analog local
bus and precision reference through multiplexers. The output
from each comparator could be routed to any of the two input
LUTs. The output of that LUT is routed to the UDB Digital System
Interface.
Figure 8-4. Analog Comparator
From
Analog
Routing
+
_^comp0
ANAIF
+
comp1
_
From
Analog
Routing
From
Analog
Routing
+
c_{_}omp2
44 44
LUT0
LUT1
44 44
LUT2
LUT3
+
comp3_{_}
From
Analog
Routing
UDBs
8.3.2 LUT
The CY8C38 family of devices contains four LUTs. The LUT is a
two input, one output lookup table that is driven by any one or
two of the comparators in the chip. The output of any LUT is
routed to the digital system interface of the UDB array. From the
digital system interface of the UDB array, these signals can be
connected to UDBs, DMA controller, I/O, or the interrupt
controller.
The LUT control word written to a register sets the logic function
on the output. The available LUT functions and the associated
control word is shown in Table 8-2.
Document Number: 001-11729 Rev. *I
Page 52 of 100
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