CY8C38 Datasheet, PDF (10/100 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC)

PRELIMINARY
PSoC^®3: CY8C38 Family Data Sheet
Figure 2-6. Example PCB Layout for 100-Pin TQFP Part for Optimal Analog Performance
VSSA
VDDD
VSSD
VDDA
VSSD
Plane
VSSA
Plane
3. Pin Descriptions
IDAC0, IDAC1, IDAC2, IDAC3. Low resistance output pin for
high current DACs (IDAC).
OpAmp0out, OpAmp1out, OpAmp2out, OpAmp3out. High
current output of uncommitted opamp^[4].
Extref0, Extref1. External reference input to the analog system.
OpAmp0-, OpAmp1-, OpAmp2-, OpAmp3-. Inverting input to
uncommitted opamp.
OpAmp0+, OpAmp1+, OpAmp2+, OpAmp3+. Noninverting
input to uncommitted opamp.
GPIO. General purpose I/O pin provides interfaces to the CPU,
digital peripherals, analog peripherals, interrupts, LCD segment
drive, and CapSense^[4].
I2C0: SCL, I2C1: SCL. I²C SCL line providing wake from sleep
on an address match. Any I/O pin can be used for I²C SCL if
wake from sleep is not required.
I2C0: SDA, I2C1: SDA. I²C SDA line providing wake from sleep
on an address match. Any I/O pin can be used for I²C SDA if
wake from sleep is not required.
Ind. Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 33 MHz crystal oscillator pin.
nTRST. Optional JTAG Test Reset programming and debug port
connection to reset the JTAG connection.
SIO. Special I/O provides interfaces to the CPU, digital periph-
erals and interrupts with a programmable high threshold voltage,
analog comparator, high sink current, and high impedance state
when the device is unpowered.
SWDCK. Serial Wire Debug Clock programming and debug port
connection.
SWDIO. Serial Wire Debug Input and Output programming and
debug port connection.
SWV. Single Wire Viewer debug output.
TCK. JTAG Test Clock programming and debug port connection.
TDI. JTAG Test Data In programming and debug port
connection.
TDO. JTAG Test Data Out programming and debug port
connection.
TMS. JTAG Test Mode Select programming and debug port
connection.
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from Vddd instead
of from a Vddio. Pins are No Connect (NC) on devices without
USB.^[2]
USBIO, D-. Provides D- connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from Vddd instead
of from a Vddio. Pins are No Connect (NC) on devices without
USB.^[2]
Vboost. Power sense connection to boost pump.
Vbat. Battery supply to boost pump.
Vcca. Output of analog core regulator and input to analog core.
Requires a 1 µF capacitor to Vssa. Regulator output not for
external use.
Vccd. Output of digital core regulator and input to digital core.
Requires a capacitor from each Vccd pin to Vssd; see Power
System on page 25. Regulator output not for external use.
Note
4. GPIOs with OpAmp outputs are not recommended for use with CapSense.
Document Number: 001-11729 Rev. *I
Page 10 of 100
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