CY8C38 Datasheet, PDF (25/100 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC)

PRELIMINARY
PSoC^®3: CY8C38 Family Data Sheet
6.2 Power System
The power system consists of separate analog, digital, and I/O supply pins, labeled Vdda, Vddd, and Vddiox, respectively. It also
includes two internal 1.8V regulators that provide the digital (Vccd) and analog (Vcca) supplies for the internal core logic. The output
pins of the regulators (Vccd and Vcca) and the Vddio pins must have capacitors connected as shown in Figure 6-2. One of the Vccd
pins must have a 1 µF ±10% X5R capacitor connected to Vssd. The other Vccd pin should have a 0.1 µF ±10% X5R capacitor
connected to Vssd. Also, a trace that is as short as possible must run between the two Vccd pins. The power system also contains a
sleep regulator, an I²C regulator, and a hibernate regulator.
Figure 6-2. PSoC Power System
Vddio2
1 µF
0.1µF
Vddd
Vddio0
I/ O Supply
I/ O Supply
Vddio0
I2C
Regulator
0.1µF
Digital
Domain
Vssd
Digital
Regulators
Sleep
Regulator
Vdda
Analog
Vcca
Regulator
Vssa
Analog
Domain
Vdda
1 µF
.
Hibernate
Regulator
I/O Supply
0.1µF
Vddio1
0.1µF
Vddd
I/O Supply
0.1µF
Vddio3
6.2.1 Power Modes
PSoC 3 devices have four different power modes. The power
modes allow a design to easily provide required functionality and
processing power while simultaneously minimizing power
consumption and maximizing battery life in low power and
portable devices.
PSoC 3 power modes, in order of decreasing power
consumption are:
„ Active
„ Alternate Active
„ Sleep
„ Hibernate
Active is the main processing mode. Its functionality is config-
urable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and Real Time Clock
functionality. The lowest power mode is hibernate, which retains
register and SRAM state, but no clocks, and allows wakeup only
from I/O pins. Figure 6-3 illustrates the allowable transitions
between power modes.
Document Number: 001-11729 Rev. *I
Page 25 of 100
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