Z9960 Datasheet, PDF (5/7 Pages) Cypress Semiconductor – 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer

Z9960
AC Electrical Characteristics V_DD = 2.5V ±5% or 3.3V ±5%, T_A = –40°C to +85°C^[7]
Symbol
Parameter
Test Condition
Min.
Typ.
Fref
Reference Input Frequency
FB_SEL = 1
16
–
FB_SEL = 0
25
–
FrefDC
Reference Input Duty Cycle
25
–
Fvco
PLL VCO Lock Range
200
–
Tlock
Maximum PLL lock Time
–
–
Tr / Tf
Output Clocks Rise / Fall
Time^[8],[9]
0.55V to 2.0V, V_DD = 3.3V
0.1
0.5V to 1.8V, V_DD = 2.5V
–
–
–
Fout
Maximum Output Frequency
Q (÷2)
100
–
FoutDC
tpZL, tpZH
tpLZ, tpHZ
TCCJ
Output Duty Cycle^[8],[9]
Output Enable Time^[8] (all
outputs)
Output Disable Time^[8] (all
outputs)
Cycle to Cycle Jitter^[8],[9]
Q (÷4)
50
–
45
50
2
–
2
–
–
±100
Tskew
Any Output to Any Output
Skew^[8],[9]
Same frequency
–
–
Different frequency
–
–
Tskew
Bank to Bank Skew
Tskew(pp) Part to Part Skew^[10]
Banks at different voltages
–
–
–
–
Tpd
Phase
TCLK or
Error^[8],[9]
PECL_CLK to
FB_IN
V_DD = 3.3V
V_DD = 2.5V
0
100
25
125
Note:
7. Parameters are guaranteed by design and characterization. Not 100% tested in production.
8. Outputs loaded with 30pF each.
9. 50Ω transmission line terminated into VDD/2.
10. Part to Part skew at a given temperature and voltage
Max.
33
50
75
400
10
1.0
–
200
100
55
10
8
–
150
300
400
450
200
225
Unit
MHz
%
MHz
ms
ns
MHz
%
ns
ns
ps
ps
ps
ps
ps
Document #: 38-07087 Rev. *C
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