Z9960 Datasheet, PDF (2/7 Pages) Cypress Semiconductor – 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer

Z9960
Pin Definition
Pin Name
PECL_CLK
PECL_CLK#
TCLK
QA(6:0)
QB(6:0)
QC(6:0)
FB_OUT
No.
3
4
2
38, 39, 40, 42,
43, 45, 46
26, 27, 28, 30,
31, 33, 34
15, 16, 18, 19,
21, 22, 23
35
SELA
SELB
SELC
FB_SEL
FB_IN
REF_SEL
OE#
V_DDA
V_DDB
V_DDC
V_DD
AV_DD
V_SSA
V_SSB
V_SSC
V_SS
9
10
11
7
47
6
14
37, 44
25, 32
13, 20
5
8
36, 41
24, 29
12, 17
1, 48
Type
I, PD
I, PU
I, PD
O
V_DDA
O
V_DDB
O
V_DDC
O
V_DD
I, PU
I, PU
I, PU
I, PU
I, PD
I, PU
I, PD
Pin Description
PECL Clock Input.
PECL Clock Input.
External Reference/Test Clock Input.
Clock Outputs. See Table 1 for frequency selections.
Clock Outputs. See Table 1 for frequency selections.
Clock Outputs. See Table 1 for frequency selections.
Feedback Clock Output. Connect to FB_IN for normal operation. The divider
ratio for this output is set by FB_SEL; see Table 1. A bypass delay capacitor at
this output will control Input Reference/ Output Banks phase relationships.
Frequency Select Inputs. These inputs select the divider ratio at QA(0:6)
outputs. See Table 1.
Frequency Select Inputs. These inputs select the divider ratio at QB(0:6)
outputs. See Table 1.
Frequency Select Inputs. These inputs select the divider ratio at QC(0:6)
outputs. See Table 1.
Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output.
See Table 1.
Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
Reference Select Input. When high, the PECL clock is selected. And when low,
TCLK is the reference clock.
Output Enable Input. When asserted low, enables all of the outputs. When
pulled high, disables to high impedance all of the outputs except FB_OUT.
Power Supply for Bank A Clock Buffers.
Power Supply for Bank B Clock Buffers.
Power Supply for Bank C Clock Buffers.
Power Supply for Core
Power Supply for PLL. When AVDD is set low, PLL is bypassed.
Common Ground for Bank A.
Common Ground for Bank B.
Common Ground for Bank C.
Common Ground.
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors
are not close to the pins, their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Document #: 38-07087 Rev. *C
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