Z9960 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer

Z9960
2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer
Features
• 2.5V or 3.3V operation
• Output frequency up to 200 MHz
• Supports PowerPC, and Pentium® processors
• 21 clock outputs: drive up to 42 clock lines
• LVPECL or LVCMOS/LVTTL clock input
• Output-to-output skew < 150 ps
• Split 2.5V/3.3V outputs
• Spread spectrum compatible
• Glitch-free output clocks transitioning
• Output disable control
• Pin-compatible with MPC9600
• Industrial temperature range: –40°C to +85°C
• 48-pin LQFP package
Table 1. Frequency Table^[1]
S
S
E
E
L
L
A QA B
0 VCO/2 0
1 VCO/4 1
QB
VCO/2
VCO/4
F
B
S
_
E
S
L
E
C QC L
0 VCO/2 0
1 VCO/4 1
FB_OUT
VCO/8
VCO/12
Block Diagram
Pin Configuration
REF_SEL
TCLK
PECL_CLK
PECL_CLK#
FB_IN
SELA
SELB
AVDD
PLL
0
0
/2
/4
REF
1
FB
1
/8
/12
A
0
DQ
1
B
0
1
DQ
SELC
C
0
1
DQ
OE#
FB
0
1
DQ
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
FB_OUT
VSS
TCLK
PECL_CLK
PECL_CLK#
VDD
REF_SEL
FB_SEL
AVDD
SELA
SELB
SELC
VSSC
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
Z9960 ³¹
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
VSSA
FB_OUT
QB0
QB1
VDDB
QB2
QB3
VSSB
QB4
QB5
QB6
VDDB
FB_SEL
Note:
1. Input frequency range: 16 MHz to 33 MHz (FB_SEL = 1), or 25 MHz to 50 MHz (FB_SEL = 0).
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07087 Rev. *C
Revised May 03, 2004