Z9960 Datasheet, PDF (3/7 Pages) Cypress Semiconductor – 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer

Z9960
Function Table
Control Pin
REF_SEL
AVDD
OE#
SELA
SELB
SELC
FB_SEL
0
TCLK
PLL Bypass, Outputs Controlled by OE#
Outputs Enabled
Output Bank A at VCO/2
Output Bank B at VCO/2
Output Bank C at VCO/2
Feedback Output at VCO/8
1
PECL_CLK
PLL Power
Outputs Disabled (except FB_OUT)
Output Bank A at VCO/4
Output Bank B at VCO/4
Output Bank C at VCO/4
Feedback Output at VCO/12
Overview
Zero Delay Buffer
The Z9960 has an integrated PLL that provides low skew and
low jitter clock outputs for high-performance microprocessors.
Three independent banks of seven outputs as well as an
independent PLL feedback output, FB_OUT, provide excep-
tional flexibility for possible output configurations. The PLL is
ensured stable operation given that the VCO is configured to
run between 200 MHz to 400 MHz. This allows a wide range
of output frequencies up to 200 MHz.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the input
reference clock set by FB_SEL select inputs; refer to Table 1.
The VCO frequency is then divided down to provide the
required output frequencies.
When used as a zero delay buffer the Z9960 will likely be in a
nested clock tree application. For these applications the
Z9960 offers a low-voltage PECL clock input as a PLL
reference. This allows the user to use LVPECL as the primary
clock distribution device to take advantage of its far-superior
skew performance. The Z9960 then can lock onto the LVPECL
reference and translate with near zero delay to low skew
outputs.
By using one of the outputs as a feedback to the PLL, the
propagation delay through the device is eliminated. The PLL
works to align the output edge, with the input reference edge
thus producing a near-zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between the inputs and outputs. Because the static
phase offset is a function of the reference clock, the Tpd of the
Z9960 is a function of the configuration used.
Document #: 38-07087 Rev. *C
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