Z9960 Datasheet, PDF (4/7 Pages) Cypress Semiconductor – 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer

Z9960
Absolute Maximum Ratings^[2]
Input Voltage Relative to V_SS:...............................V_SS – 0.3V
Input Voltage Relative to V_DD: ............................. V_DD + 0.3V
Storage Temperature: .................................-65°C to + 150°C
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V_IN and V_OUT should be constrained to
the range
Operating Temperature: ................................-40°C to + 85°C
Maximum ESD Protection................................................ 2kV
Maximum Power Supply: ................................................5.5V
V_SS < (V_IN or V_OUT) < V_DD.
Unused inputs must always be tied to an appropriate logic
voltage level (either V_SS or V_DD).
Maximum Input Current:..................................................± 20mA
Note:
2. The voltage on any input or I/O or pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Characteristics V_DD = 2.5V ±5%, T_A = –40°C to +85°C
Parameter
V_IL[3]
V_IH[3]
V_PP
VCMR^[4]
I_IL[5]
I_IH[5]
V_OL[6]
V_OH[6]
I_DD
C_IN
Description
Input Low Voltage
Input High Voltage
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range
PECL_CLK
Input Low Current (@ V_IL = V_SS)
Input High Current (@ V_IH =
V_DD)
Output Low Voltage
Output High Voltage
Quiescent Supply Current
Input Pin Capacitance
Test Condition
I_OL = 15 mA
I_OH = –15 mA
V_DD and AV_DD
Min.
V_SS
1.7
500
V_DD –1.4
–
–
–
1.8
–
–
Typ.
–
–
–
–
–
–
–
–
10
4
Max.
0.7
V_DD
1000
Unit
V
V
mV
V_DD –0.6
V
–120
µA
120
µA
0.6
V
V
13
mA
–
pF
DC Electrical Characteristics V_DD = 3.3V +5%, T_A = –40°C to +85°C
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
V_IL[3]
V_IH[3]
Input Low Voltage
Input High Voltage
V_SS
–
0.8
V
2.0
–
V_DD
V
V_PP
Peak-to-Peak Input Voltage
PECL_CLK
500
–
1000
mV
VCMR^[4]
I_IL[5]
I_IH[5]
V_OL[6]
V_OH[6]
Common Mode Range PECL_CLK
Input Low Current (@ V_IL = V_SS)
Input High Current (@ V_IH = V_DD)
Output Low Voltage
Output High Voltage
I_OL = 24 mA
I_OH = –24 mA
V_DD –1.4
–
V_DD –0.6
V
–
–
–120
µA
–
–
120
µA
–
–
0.55
V
2.4
–
–
V
I_DD
Quiescent Supply Current
V_DD and AV_DD
–
15
20
mA
C_IN
Input Pin Capacitance
–
4
–
pF
Notes:
3. The LVCMOS inputs threshold is at 30% of V_DD.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when HIGH input is within the VCMR range
and the input lies within the V_PP specification.
5. Inputs have pull-up/pull-down resistors that affect input current.
6. Driving series or parallel terminated 50Ω (or 50Ω to V_DD/2) transmission lines.
Document #: 38-07087 Rev. *C
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