CY7C43644AV Datasheet, PDF (5/37 Pages) Cypress Semiconductor – 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

CY7C43644AV
CY7C43664AV
CY7C43684AV
Pin Definitions (continued)
Signal Name
EFB/ORB
ENA
ENB
FFA/IRA
FFB/IRB
FS1/SEN
FS0/SD
MBA
MBB
MBF1
MBF2
MRS1
Description
Port B Empty/
Output Ready
Flag
Port A Enable
Port B Enable
Port A Full/Input
Ready Flag
Port B Full/Input
Ready Flag
Flag Offset
Select 1/Serial
Enable
Flag Offset
Select 0/Serial
Data
Port A Mailbox
Select
Port B Mailbox
Select
Mail1 Register
Flag
Mail2 Register
Flag
FIFO1 Master
Reset
I/O
Function
O This is a dual-function pin. In the CY Standard mode, the EFB function is selected.
EFB indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
function is selected. ORB indicates the presence of valid data on B_0–35 outputs
available for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of
CLKB.
I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to Read or Write
data on Port A.
I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to Read or Write
data on Port B.
O This is a dual-function pin. In the CY Standard mode, the FFA function is selected.
FFA indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA
function is selected. IRA indicates whether or not there is space available for writing to
the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
O This is a dual-function pin. In the CY Standard mode, the FFB function is selected.
FFB indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB
function is selected. IRB indicates whether or not there is space available for writing to
the FIFO2 memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.
I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register
programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select
the flag offset programming method. Three offset register programming methods are
I
available: automatically load one of three preset values (8, 16, or 64), parallel load from
Port A, and serial load. When serial load is selected for flag offset register programming,
FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into
the X and Y registers. The number of bit Writes required to program the offset registers
is 40 for the CY7C43644AV, 48 for the CY7C43664AV, and 56 for the CY7C43684AV.
The first bit Write stores the Y-register MSB and the last bit Write stores the X-register
LSB.
I A HIGH level on MBA chooses a mailbox register for a Port A Read or Write
operation. When a Read operation is performed on Port A, a HIGH level on MBA
selects data from the Mail2 register for output and a LOW level selects FIFO2 output
register data for output. When a Write operation is performed on port A, a HIGH level
on MBA will write the data into Mail1 register, while a LOW level will write the data into
FIFO1.
I A HIGH level on MBB chooses a mailbox register for a Port B Read or Write
operation. When a Read operation is performed on Port B, a HIGH level on MBB
selects data from the Mail1 register for output and a LOW level selects FIFO1 output
register data for output. When a Write operation is performed on port B, a HIGH level
on MBB will write the data into Mail2 register, while a LOW level will write the data into
FIFO2.
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the
Mail1 register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is
set HIGH by a LOW-to-HIGH transition of CLKB when a Port B Read is selected and
MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set
HIGH by a LOW-to-HIGH transition of CLKA when a Port A Read is selected and MBA
is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
I A LOW on this pin initializes the FIFO1 Read and Write pointers to the first location
of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1
selects the programming method (serial or parallel) and one of three programmable
flag default offsets for FIFO1. It also configures Port B for bus size and endian
arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transi-
tions of CLKB must occur while MRS1 is LOW.
Document #: 38-06025 Rev. *C
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