CY7C43644AV Datasheet, PDF (35/37 Pages) Cypress Semiconductor – 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

Switching Waveforms (continued)
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)^[64]
CY7C43644AV
CY7C43664AV
CY7C43684AV
CLKB
CSB
[34]
W/RB
MBB
ENB
B_0–35
CLKA
MBF2
t_ENS t_ENH
t_ENS t_ENH
t_ENS t_ENH
t_ENS ^tENH
t_DS t_DH
W1
t_PMF
t_PMF
CSA
[32]
W/RA
MBA
ENA
A_0−35
t_EN
t_MDV
FIFO2 Output
Register
FIFO1 Retransmit Timing ^{[65, 66, 67, 68,69]}
CLKA
t_PMR
t_ENS
t_ENH
t_DIS
W1 (Remains valid in Mail2 Register after Read)
CLKB
RT1
ENB
EFB/FFA
t_RSTS
t_RSTH
t_RTR
Notes:
64. If Port B is configured for word size, data can be written to the Mail2 register using B_0–17 (B_18–35 are “Don’t Care” inputs). In this first case A_0–17 will have valid
data (A_18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B_0–8 (B_9–35 are “Don’t Care” inputs). In
this second case, A_0–8 will have valid data (A_9–35 will be indeterminate).
65. Retransmit is performed in the same manner for FIFO2.
66. Clocks are free running in this case. CY standard mode only. Write operation should be prohibited one Write clock cycle before the falling edge of RT1, and
during the retransmit operation, i.e, when RT1 is LOW and t_RTR after the RT1 rising edge.
67. The Empty and Full flags may change state during Retransmit as a result of the offset of the Read and Write pointers, but the Empty and Full flags will be valid
at t_RTR.
68. For the AEA, AEB, AFA,and AFB flags, two clock cycle are necessary after t_RTR to update these flags.
69. The number of 36-/18-/9-bit words written into the FIFO should be less than full depth minus 2/4/8 words between the reset of the FIFO (master or partial) and
the Retransmit setup.
Document #: 38-06025 Rev. *C
Page 35 of 37