CY7C43644AV Datasheet, PDF (30/37 Pages) Cypress Semiconductor – 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

Switching Waveforms (continued)
IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)^[48]
CLKA
t_CLK
t_CLKH t_CLKL
CSA
W/RA
MBA
ENA
LOW
LOW
LOW
t_ENS t_ENH
EFA/ORA HIGH
tA
A_0–35
CLKB
FFB/IRB
Previous Word in FIFO2
Next Word From FIFO2
Output Register
t_SKEW1^{[49] tCLKH tCLK}
FIFO2 Full
t_CLK
t_WFF
t_WFF
CSB
LOW
W/RB
MBB
ENB
B_0–35
LOW
t_ENS t_ENH
t_EN t_ENH
t_DS t_DH
To FIFO2
CY7C43644AV
CY7C43664AV
CY7C43684AV
Notes:
48. If Port B size is word or byte, IRB is set LOW by the last word or byte Write of the long-word, respectively.
49. t_SKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than t_SKEW1, then the transition of IRB HIGH may occur one CLKB cycle later than shown.
Document #: 38-06025 Rev. *C
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