CY7C43644AV Datasheet, PDF (25/37 Pages) Cypress Semiconductor – 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

Switching Waveforms (continued)
EFB Flag Timing and First Data Read Fall Through when FIFO1 is
Empty (CY Standard Mode) ^[40]
t_CLK
t_CLKH ^tCLKL
CLKA
CSA
W/RA
MBA
ENA
LOW
HIGH
t_EN t_ENH
t_ENSt_ENH
FFA/IRA
HIGH
A_0–35
t_DS t_DH
W1
CLKB
t_CLKH t_CLKL
t_SKEW1^[42]
EFB/ORB _{FIFO1 Empty}
t_CLK
t_REF
t_REF
CSB
LOW
W/RB
HIGH
MBB
ENB
B_0–35
LOW
t_EN t_ENH
t_A
CY7C43644AV
CY7C43664AV
CY7C43684AV
W1
Note:
42. t_SKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than t_SKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Document #: 38-06025 Rev. *C
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