CY7C43644AV Datasheet, PDF (1/37 Pages) Cypress Semiconductor – 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

CY7C43644AV
CY7C43664AV
CY7C43684AV
3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with
Bus Matching
Features
• 3.3V high-speed, low-power, bidirectional, First-In
First-Out (FIFO) memories w/ bus matching capabilities
• 1K × 36 × 2 (CY7C43644AV)
• 4K × 36 × 2 (CY7C43664AV)
• 16K × 36 × 2 (CY7C43684AV)
• 0.25-micron CMOS for optimum speed/power
• High-speed 133-MHz operation (7.5-ns Read/Write
cycle times)
• Low power
— I_CC= 60 mA
— I_SB= 10 mA
Table 1.
• Fully asynchronous and simultaneous Read and Write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel and Serial Programmable Almost Full and
Almost Empty flags
• Retransmit function
• Standard or FWFT user selectable mode
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Easily expandable in width and depth
Logic Block Diagram
CLKA
CSA
W/RA
ENA
MBA
RT2
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A_0–35
EFA/ORA
AEA
Port A
Control
Logic
FIFO1,
Mail1
Reset
Logic
36
MBF2
Mail1
Register
1K/4K/16K
× 36
Dual Ported
Memory
(FIFO 1)
Write
Pointer
Read
Pointer
Status
Flag Logic
Programmable
Flag Offset
Registers
Timing
Mode
Status
Flag Logic
Write
Pointer
Read
Pointer
1K/4K/16K
× 36
Dual Ported
Memory
(FIFO 2)
Mail2
Register
Port B
Control
Logic
MBF1
CLKB
CSB
W/RB
ENB
MBB
RTI
BM
SIZE
36
FIFO1,
Mail1
Reset
Logic
EFB/ORB
AEB
B_0–35
BE/FWFT
FFB/IRB
AFB
MRS2
PRS2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06025 Rev. *C
Revised December 26, 2002