C9630 Datasheet, PDF (5/18 Pages) Cypress Semiconductor – PC133 Clock Generator for SiS630/Pentium III & SiS540/Socket7 Applications

APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium^®III & SiS540/Socket7 Applications
2-Wire SMBus Control Interface
The 2-wire control interface implements a read/write slave only interface according to SMBus specification (IC12, 1996).
The device can be read back by using standard SMBus command bytes. Sub addressing is not supported, thus all
preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock
output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported.
During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is
high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer
cycle is a 7-bit address with a Read/Write bit (R/W#) as the LSB. R/W# = 1 in read mode. R/W# = 0 in write mode.
A maximum of 10 bytes of data may be written/Read Data is transferred MSB first at a max rate of 100kbits/S.The
device will not respond to any other control interface conditions.
In the Write mode (See fig6A, p.9), the clock gen. acknowledges Address Byte, D2, then receives two additional bytes:
1) “Command Code “ byte, and
2) “Byte Count” byte. Must be programmed to FF for correct operation.
Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.
Subsequently, the below-described sequence (Byte 0, Byte 1, Byte2,) will be valid and acknowledged.
In the Read Mode (See fig6B, p.9), the clock gen. acknowledges Address D3, and immediately transmits data starting
with Byte count, then Byte 0, 1, 2, ... After each transmitted byte, this device waits for an acknowledge before
transmitting the next byte.
Serial Control Registers
NOTE: Power up conditions for each bit are listed in the “@Pup” column.
Byte 0: Frequency, Function Select Register
Bit @Pup Pin# Description, see page 8 for SSCG description.
7
0
n/a S4 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1
6
0
n/a S2 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1
5
0
n/a S1 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1
4
0
n/a S0 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1
3
0
n/a 0 = frequency selected by hardware, pins
1 = frequency selection via SMBus byte0.
2,7,8,26
bits 4,5,6,2,7
2
0
n/a S3 (for frequency table 3, selection by software via SMBus), selection valid if bit3 = 1
1
0
n/a 0 = Spread Spectrum disabled
1 = Spread spectrum enabled
0
0
n/a 0 = Running
1 = Test mode.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: [phone], Fax: [phone]
http://www.cypress.com
Document#: 38-07035 Rev. **
05/02/2001
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