C9630 Datasheet, PDF (2/18 Pages) Cypress Semiconductor – PC133 Clock Generator for SiS630/Pentium III & SiS540/Socket7 Applications

APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium^®III & SiS540/Socket7 Applications
Pin Description
PIN No.
Pin Name PWR I/O
Description
2
S3/ REF0
VDD I/O 3.3V 14.318 MHz clock output. This Is a power on bi-directional pin.
During power up, this pin is an input “S3” for setting the CPU
frequency (see table1, page 1) (see app note, page 5). When the
power reaches the rail, this pin becomes a buffered output of the
signal applied at Xin (typically 14.318 MHz).
48
REF1
VDD O This pin is a buffered output of the signal applied at Xin (typically
14.318)
4
XIN
VDD I 14.318MHz Crystal input
5
XOUT
VDD O 14.318MHz Crystal output
7
S1/ PCI0*
VDD I/O This is a power on bi-directional pin. During power up, this pin is an
input “S1” for setting the CPU frequency (see table1, page 1) (see
app not, page 5). When the power reaches the rail, this pin becomes
a PCI0 clock output.
8
S2/ PCI1*
VDD I/O This is a power on bi-directional pin. During power up, this pin is an
input “S2” for setting the CPU frequency (see table1, page 1) (see
app not, page 5). When the power reaches the rail, this pin becomes
a PCI1 clock output.
9,11,12,13, PCI(2:6)
14
VDD O 3.3V PCI clock outputs.
25
24/48MHz
VDD O This pin is programmable to 24MHz or 48 MHz clock output through
SMBus. It defaults to 24MHz at power up.
26
S0 / 48MHz* VDD I/O This is a power on bi-directional pin. During power up, this pin is an
input “S0” for setting the CPU frequency (see table1, page 1) (see
app note, page 5). When the power reaches the rail, this pin becomes
a 48MHz clock output. This clock conforms to the USB spec. of
+167ppm.
28
SDATA
VDD I SMBus compatible SDATA input. Has an internal pull-up (>100KΩ)
29
SCLK
VDD I SMBus compatible SCLK input. Has an internal pull-up (>100KΩ)
17,18,20,21, SDRAM(0:13) VDD O 3.3V SDRAM clock outputs. See table1, p.1 for frequency selection.
28,29,31,32,
34,35,37,38,
40,41
43,45,46 CPU(0:2)
VDDC O 2.5V or 3.3V Host bus clock outputs. See table 1, page 1 for
frequency selection.
1,6,15,19, VDD
27, 30,36,42
-
3.3V Common Power Supply
47
VDDC
-
2.5V or 3.3V Power Supply’s for CPU (0:2) clock outputs.
3,10,16,22, VSS
33,39,44
-
Common Ground pin.
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
*Note: These pins have pulldown resistors, typical value 250 Ω.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: [phone], Fax: [phone]
http://www.cypress.com
Document#: 38-07035 Rev. **
05/02/2001
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