CY7C63923-PVXC Datasheet, PDF (46/68 Pages) Cypress Semiconductor – enCoRe™ II Low-Speed USB Peripheral Controller

CY7C63310
CY7C638xx
CY7C639xx
17.4.3 Interrupt Vector Clear Register
Table 17-9. Interrupt Vector Clear Register (INT_VC) [0xE2] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Pending Interrupt [7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
The Interrupt Vector Clear Register (INT_VC) holds the interrupt vector for the highest priority pending interrupt when read, and
when written will clear all pending interrupts
Bit [7:0]: Pending Interrupt [7:0]
8-bit data value holds the interrupt vector for the highest priority pending interrupt. Writing to this register will clear all pending
interrupts.
18.0 USB/PS2 Transceiver
Although the USB transceiver has features to assist in inter-
facing to PS/2 these features are not controlled using these
registers. These registers only control the USB interfacing
features. PS/2 interfacing options are controlled by the D+/D–
GPIO Configuration register (See Section Table 14.2.15).
18.1 USB Transceiver Configuration
Table 18-1. USB Transceiver Configure Register (USBXCR) [0x74] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
USB Pull-up
Enable
Reserved
USB Force State
Read/Write
R/W
–
–
–
–
–
–
R/W
Default
0
0
0
0
0
0
0
0
Bit 7: USB Pull-up Enable
0 = Disable the pull-up resistor on D–
1 = Enable the pull-up resistor on D–. This pull-up is to V_CC IF VREG is not enabled or to the internally generated 3.3V when
VREG is enabled
Bit [6:1]: Reserved
Bit 0: USB Force State
This bit allows the state of the USB I/O pins D- and D+ to be forced to a state while USB is enabled
0 = Disable USB Force State
1 = Enable USB Force State. Allows the D- and D+ pins to be controlled by P1.1 and P1.0 respectively when the USBIO is in
USB mode. Refer to Section 14.2.15 for more information
Document 38-08035 Rev. *E
Page 46 of 68