CY7C63923-PVXC Datasheet, PDF (18/68 Pages) Cypress Semiconductor – enCoRe™ II Low-Speed USB Peripheral Controller

CY7C63310
CY7C638xx
CY7C639xx
The Internal 32-KHz Low-power Oscillator accuracy ranges
from –85% to +120% (between 0°–70° C).
For applications that require a higher clock accuracy, the
CY7C639xx part can optionally be sourced from an external
crystal oscillator. When operating in USB mode, the supplied
crystal oscillator must be either 12 MHz or 24 MHz in order for
the USB blocks to function properly. In non-USB mode, the
external oscillator can be up to 24 MHz.
10.1 Clock Architecture Description
The enCoRe II clock selection circuitry allows the selection of
independent clocks for the CPU, USB, Interval Timers and
Capture Timers.
On the CY7C639xx, the external oscillator can be sourced by
the crystal oscillator or when the crystal oscillator is disabled it
is sourced directly from the CLKIN pin. The external crystal
oscillator is fed through the EFTB block, which can optionally
be bypassed.
The CPU clock, CPUCLK, can be sourced from the external
crystal oscillator or the Internal 24-MHz Oscillator. The
selected clock source can optionally be divided by 2ⁿ where n
is 0-5,7 (see Table 10-5).
USBCLK, which must be 12 MHz for the USB SIE to function
properly, can be sourced by the Internal 24-MHz Oscillator or
the external crystal oscillator. An optional divide by two allows
the use of 24-MHz source.
The Interval Timer clock (ITMRCLK), can be sourced from the
external crystal oscillator, the Internal 24-MHz Oscillator, the
Internal 32-KHz Low-power Oscillator, or from the timer
capture clock (TCAPCLK). A programmable prescaler of 1, 2,
3, 4 then divides the selected source.
The Timer Capture clock (TCAPCLK) can be sourced from the
external crystal oscillator, Internal 24-MHz Oscillator, or the
Internal 32-KHz Low-power Oscillator.
When it is not being used by the external crystal oscillator, the
CLKOUT pin can be driven from one of many sources. This is
used for test and can also be used in some applications. The
sources that can drive the CLKOUT are:
• CLKIN after the optional EFTB filter
• Internal 24-MHz Oscillator
• Internal 32-KHz Low-power Oscillator
• CPUCLK after the programmable divider
10.1.1 Clock Control Registers
10.1.2 Internal Clock Trim
Table 10-1. IOSC Trim (IOSCTR) [0x34] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
foffset[2:0]
Gain[4:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
D
D
D
D
D
The IOSC Calibrate register is used to calibrate the internal oscillator. The reset value is undefined but during boot the SROM
writes a calibration value that is determined during manufacturing test. This value should not require change during normal use.
This is the meaning of ‘D’ in the Default field
Bit [7:5]: foffset [2:0]
This value is used to trim the frequency of the internal oscillator. These bits are not used in factory calibration and will be zero.
Setting each of these bits causes the appropriate fine offset in oscillator frequency.
foffset bit 0 = 7.5 KHz
foffset bit 1 = 15 KHz
foffset bit 2 = 30 KHz
Bit [4:0]: Gain [4:0]
The effective frequency change of the offset input is controlled through the gain input. A lower value of the gain setting increases
the gain of the offset input. This value sets the size of each offset step for the internal oscillator. Nominal gain change
(KHz/offsetStep) at each bit, typical conditions (24 MHz operation):
Gain bit 0 = –1.5 KHz
Gain bit 1 = –3.0 KHz
Gain bit 2 = –6 KHz
Gain bit 3 = –12 KHz
Gain bit 4 = –24 KHz
Document 38-08035 Rev. *E
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