CY7C63923-PVXC Datasheet, PDF (41/68 Pages) Cypress Semiconductor – enCoRe™ II Low-Speed USB Peripheral Controller

CY7C63310
CY7C638xx
CY7C639xx
16.1.13 Capture Interrupt Status
Table 16-13. Capture Interrupt Status (TCAPINTS) [0x2C] [R/W]
Bit #
7
6
5
4
Field
Reserved
Read/Write
–
–
–
–
Default
0
0
0
0
Bit [7:4]: Reserved
Bit 3: Cap1 Fall Active
0 = No event
1 = A falling edge has occurred on Cap1
Bit 2: Cap1 Rise Active
0 = No event
1 = A rising edge has occurred on Cap1
Bit 1: Cap0 Fall Active
0 = No event
1 = A falling edge has occurred on Cap0
Bit 0: Cap0 Rise Active
0 = No event
1 = A rising edge has occurred on Cap0
3
Cap1 Fall
Active
R/W
0
2
Cap1 Rise
Active
R/W
0
1
Cap0 Fall
Active
R/W
0
0
Cap0 Rise
Active
R/W
0
17.0 Interrupt Controller
The interrupt controller and its associated registers allow the
user’s code to respond to an interrupt from almost every
functional block in the enCoRe II devices. The registers
associated with the interrupt controller allow interrupts to be
disabled either globally or individually. The registers also
provide a mechanism by which a user may clear all pending
and posted interrupts, or clear individual posted or pending
interrupts.
The following table lists all interrupts and the priorities that are
available in the enCoRe II devices.
Table 17-1. Interrupt Numbers, Priorities, Vectors
Interrupt
Priority
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Interrupt
Address
Name
0000h Reset
0004h POR/LVD
0008h INT0
000Ch SPI Transmitter Empty
0010h SPI Receiver Full
0014h GPIO Port 0
0018h GPIO Port 1
001Ch INT1
0020h EP0
0024h EP1
0028h EP2
002Ch USB Reset
0030h USB Active
0034h 1-mS Interval timer
0038h Programmable Interval Timer
003Ch Timer Capture 0
0040h Timer Capture 1
Table 17-1. Interrupt Numbers, Priorities, Vectors (contin-
Interrupt
Priority
17
18
19
20
21
22
23
Interrupt
Address
0044h
0048h
004Ch
0050h
0054h
0058h
005Ch
Name
16-bit Free Running Timer Wrap
INT2
PS2 Data Low
GPIO Port 2
GPIO Port 3
GPIO Port 4
Reserved
24
0060h Reserved
25
0064h Sleep Timer
17.1 Architectural Description
An interrupt is posted when its interrupt conditions occur. This
results in the flip-flop in Figure 17-1 clocking in a ‘1’. The
interrupt will remain posted until the interrupt is taken or until
it is cleared by writing to the appropriate INT_CLRx register.
A posted interrupt is not pending unless it is enabled by setting
its interrupt mask bit (in the appropriate INT_MSKx register).
All pending interrupts are processed by the Priority Encoder to
determine the highest priority interrupt which will be taken by
the M8C if the Global Interrupt Enable bit is set in the CPU_F
register.
Disabling an interrupt by clearing its interrupt mask bit (in the
INT_MSKx register) does not clear a posted interrupt, nor
does it prevent an interrupt from being posted. It simply
prevents a posted interrupt from becoming pending.
Nested interrupts can be accomplished by re-enabling inter-
rupts inside an interrupt service routine. To do this, set the IE
bit in the Flag Register.
A block diagram of the enCoRe II Interrupt Controller is shown
in Figure 17-1.
Document 38-08035 Rev. *E
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