CY7C63923-PVXC Datasheet, PDF (34/68 Pages) Cypress Semiconductor – enCoRe™ II Low-Speed USB Peripheral Controller

CY7C63310
CY7C638xx
CY7C639xx
Table 14-18. P3 Configuration (P3CR) [0x16] [R/W] (continued)
This register exists in CY7C638xx and CY7C639xx. In CY7C638xx this register controls the operation of pins P3.0–P3.1. In the
CY7C639xx, this register controls the operation of pins P3.0–P3.7
The 50-mA sink drive capability is only available on pin P3.7 and only on the CY7C639xx. In the CY7C638xx, only 8-mA sink
drive capability is available on this pin regardless of the setting of the High Sink bit
14.2.23 P4 Configuration
Table 14-19. P4 Configuration (P4CR) [0x17] [R/W]
Bit #
7
6
5
4
3
2
Field
Reserved
Int Enable
Int Act Low
TTL Thresh
Reserved
Open Drain
Read/Write
–
R/W
R/W
R/W
–
R/W
Default
0
0
0
0
0
0
This register exists only in the CY7C639xx. This register controls the operation of pins P4.0–P4.3
1
Pull-up Enable
R/W-
0
0
Output Enable
R/W
0
15.0 Serial Peripheral Interface (SPI)
The SPI Master/Slave Interface core logic runs on the SPI
clock domain, making its functionality independent of system
clock speed. SPI is a four pin serial interface comprised of a
clock, an enable and two data pins.
15.1 SPI Data Register
Table 15-1. SPI Data Register (SPIDATA) [0x3C] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
SPIData[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
When read, this register returns the contents of the receive buffer. When written, it loads the transmit holding register
Bit [7:0]: SPI Data [7:0]
When an interrupt occurs to indicate to firmware that a byte of
receive data is available, or the transmitter holding register is
empty, firmware has 7 SPI clocks to manage the buffers—to
empty the receiver buffer, or to refill the transmit holding
register. Failure to meet this timing requirement will result in
incorrect data transfer.
Document 38-08035 Rev. *E
Page 34 of 68