CY7C68013 Datasheet, PDF (42/48 Pages) Cypress Semiconductor – EZ-USB FX2 USB Microcontroller

CY7C68013
9.16.3 Sequence Diagram of a Single and Burst Asynchronous Read
FIFOADR
SLRD
SLCS
FLAGS
DATA
SLOE
t_SFA
t_FAH
t=0
t_RDpwl t_RDpwh
t=2
t=3
t_SFA
t_FAH
T=0
t_RDpwl t_RDpwh
t_RDpwl t_RDpwh
t_RDpwl t_RDpwh
T=2
T=3
T=4
T=5
T=6
t_XFLG
t_XFLG
Data (X)
Driven
t_XFD
N
t_OEon
t_OEoff
N
t_OEon
t_XFD
N+1
t_XFD
N+2
t_XFD
N+3
t_OEoff
t=1
t=4
T=1
T=7
Figure 9-19. Slave FIFO Asynchronous Read Sequence and Timing Diagram
FIFO POINTER
SLOE
N
SLRD
SLRD
SLOE
SLOE
SLRD
SLRD
SLRD
SLRD
N
N
N+1
N+1
N+1
N+1
N+2
N+2
N+3
SLOE
N+3
FIFO DATA BUS Not Driven
Driven: X
N
N
Not Driven
N
N+1
N+1
N+2
N+2
Not Driven
Figure 9-20. Slave FIFO Asynchronous Read Sequence of Events Diagram
Figure 9-19 diagrams the timing relationship of the SLAVE
FIFO signals during an asynchronous FIFO read. It shows a
single read followed by a burst read.
• At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
• At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
• At t = 2, SLRD is asserted. The SLRD must meet the
minimum active pulse of t_RDpwl and minimum de-active
pulse width of t_RDpwh. If SLCS is used then, SLCS must be
in asserted with SLRD or before SLRD is asserted (i.e., the
SLCS and SLRD signals must both be asserted to start a
valid read condition).
• The data that will be driven, after asserting SLRD, is the
updated data from the FIFO. This data is valid after a propa-
gation delay of t_XFD from the activating edge of SLRD. In
Figure 9-19, data N is the first valid data read from the FIFO.
For data to appear on the data bus during the read cycle
(i.e., SLRD is asserted), SLOE MUST be in an asserted
state. SLRD and SLOE can also be tied together.
The same sequence of events is also shown for a burst read
marked with T = 0 through 5. Note: In burst read mode, during
SLOE is assertion, the data bus is in a driven state and outputs
the previous data. Once SLRD is asserted, the data from the
FIFO is driven on the data bus (SLOE must also be asserted)
and then the FIFO pointer is incremented.
Document #: 38-08012 Rev. *E
Page 42 of 48