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CY7C68013 Datasheet, PDF (1/48 Pages) Cypress Semiconductor – EZ-USB FX2 USB Microcontroller | |||
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CY7C68013
EZ-USB FX2⢠USB Microcontroller
1.0 EZ-USB FX2 Features
⢠Supports bus-powered applications by using renumer-
ation
⢠Single-chip integrated USB 2.0 Transceiver, SIE, and
Enhanced 8051 Microprocessor
⢠Software: 8051 code runs from:
â Internal RAM, which is downloaded via USB
â Internal RAM, which is loaded from EEPROM
â External memory device (128 pin package
⢠Four programmable BULK/INTERRUPT/
ISOCHRONOUS endpoints
â Buffering options: double, triple and quad
⢠8- or 16-bit external data interface
⢠GPIF
â Allows direct connection to most parallel interface
â Programmable waveform descriptors and configu-
ration registers to define waveforms
â Supports multiple Ready (RDY) inputs and Control
(CTL) outputs
⢠Integrated, industry standard enhanced 8051:
⢠3.3V operation
⢠Smart Serial Interface Engine
⢠Vectored USB interrupts
⢠Separate data buffers for the SETUP and DATA portions
of a CONTROL transfer
⢠Integrated I2C-compatible controller, runs at 100 or 400
kHz
⢠48-MHz, 24-MHz, or 12-MHz 8051 operation
⢠Four integrated FIFOs
â Brings glue and FIFOs inside for lower system cost
â Automatic conversion to and from 16-bit buses
â Master or slave operation
â FIFOs can use externally supplied clock or asyn-
chronous strobes
â Easy interface to ASIC and DSP ICs
⢠Special autovectors for FIFO and GPIF interrupts
⢠Up to 40 general-purpose I/Os
â Up to 48-MHz clock rate
â Four clocks per instruction cycle
â Two USARTS
â Three counter/timers
⢠Four package optionsâ128-pin TQFP, 100-pin TQFP,
56-pin QFN and 56-pin SSOP
⢠Four packages are defined for the family: 56 SSOP, 56
QFN, 100 TQFP, and 128 TQFP
â Expanded interrupt system
â Two data pointers
24-MHz
Ext. XTAL
High-performance micro
using standard tools
with lower-power options
FX2
/0.5
VCC
x20 /1.0
PLL /2.0
1.5k
connected for
full speed
D+
Dâ
Integrated
full- and high-speed
XCVR
USB
2.0
XCVR
CY
Smart
USB
1.1/2.0
Engine
8051 Core
12/24/48 MHz,
four clocks/cycle
8.5 kB
RAM
I2C
Compatible
Master
Additional I/Os (24)
ADDR (9)
GPIF
RDY (6)
CTL (6)
Abundant I/O
including two USARTS
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
4 kB
8/16
FIFO
Up to 96 MBytes/s
burst rate
Enhanced USB core
Simplifies 8051 core
âSoft Configurationâ
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation â¢
Document #: 38-08012 Rev. *E
3901 North First Street ⢠San Jose, CA 95134 ⢠408-943-2600
Revised February 8, 2005
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