CY7C68013 Datasheet, PDF (18/48 Pages) Cypress Semiconductor – EZ-USB FX2 USB Microcontroller

CY7C68013
Table 4-1. FX2 Pin Descriptions (continued)^[5]
128 100 56 56
TQFP TQFP SSOP QFN Name
Type
92 74
47 40 PA7 or
FLAGD or
SLCS#
I/O/Z
Port B
44 34
25 18 PB0 or
FD[0]
I/O/Z
45 35 26 19 PB1 or
FD[1]
I/O/Z
46 36 27 20 PB2 or
FD[2]
I/O/Z
47 37 28 21 PB3 or
TXD1 or
FD[3]
54 44 29 22 PB4 or
FD[4]
I/O/Z
I/O/Z
55 45 30 23 PB5 or
FD[5]
I/O/Z
56 46 31 24 PB6 or
FD[6]
I/O/Z
57 47 32 25 PB7 or
FD[7]
I/O/Z
PORT C
72 57
73 58
74 59
75 60
76 61
PC0 or
I/O/Z
GPIFADR0
PC1 or
I/O/Z
GPIFADR1
PC2 or
I/O/Z
GPIFADR2
PC3 or
I/O/Z
GPIFADR3
PC4 or
I/O/Z
GPIFADR4
Default
Description
I
(PA7)
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and PORTACFG.7 bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status flag signal.
SLCS# gates all other slave FIFO enable/strobes
I
(PB0)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
I
(PB1)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
I
(PB2)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
I
(PB3)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
I
(PB4)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
I
(PB5)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
I
(PB6)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
I
(PB7)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by PORTCCFG.0
(PC0) PC0 is a bidirectional I/O port pin.
GPIFADR0 is a GPIF address output pin.
I Multiplexed pin whose function is selected by PORTCCFG.1
(PC1) PC1 is a bidirectional I/O port pin.
GPIFADR1 is a GPIF address output pin.
I Multiplexed pin whose function is selected by PORTCCFG.2
(PC2) PC2 is a bidirectional I/O port pin.
GPIFADR2 is a GPIF address output pin.
I Multiplexed pin whose function is selected by PORTCCFG.3
(PC3) PC3 is a bidirectional I/O port pin.
GPIFADR3 is a GPIF address output pin.
I Multiplexed pin whose function is selected by PORTCCFG.4
(PC4) PC4 is a bidirectional I/O port pin.
GPIFADR4 is a GPIF address output pin.
Document #: 38-08012 Rev. *E
Page 18 of 48