CY7C68013 Datasheet, PDF (23/48 Pages) Cypress Semiconductor – EZ-USB FX2 USB Microcontroller

CY7C68013
5.0 Register Summary
FX2 register bit definitions are described in the FX2 TRM in
greater detail.
Table 5-1. FX2 Register Summary
Hex Size Name
Description
GPIF Waveform Memories
E400 128 WAVEDATA
GPIF Waveform Descriptor
0, 1, 2, 3 data
E480 384 reserved
GENERAL CONFIGURATION
E600 1 CPUCS
CPU Control & Status
E601 1 IFCONFIG
Interface Configuration
(Ports, GPIF, slave FIFOs)
E602 1 PINFLAGSAB^[6] Slave FIFO FLAGA and
FLAGB Pin Configuration
E603 1 PINFLAGSCD^[6] Slave FIFO FLAGC and
FLAGD Pin Configuration
E604 1 FIFORESET^[6]
Restore FIFOS to default
state
E605 1 BREAKPT
Breakpoint Control
E606 1 BPADDRH
Breakpoint Address H
E607 1 BPADDRL
Breakpoint Address L
E608 1 UART230
230 Kbaud internally
generated ref. clock
E609 1 FIFOPINPOLAR^[6] Slave FIFO Interface pins
polarity
E60A 1 REVID
Chip Revision
b7
D7
0
IFCLKSRC
FLAGB3
FLAGD3
NAKALL
0
A15
A7
0
0
rv7
E60B 1 REVCTL^[6]
Chip Revision Control
0
UDMA
E60C 1 GPIFHOLDTIME MSTB Hold Time (for UDMA)
0
3 reserved
b6
b5
b4
b3
D6
D5
D4
D3
0
PORTCSTB CLKSPD1 CLKSPD0
3048MHZ IFCLKOE IFCLKPOL ASYNC
FLAGB2 FLAGB1 FLAGB0 FLAGA3
FLAGD2 FLAGD1 FLAGD0 FLAGC3
0
0
0
EP3
0
0
0
BREAK
A14
A13
A12
A11
A6
A5
A4
A3
0
0
0
0
0
PKTEND
SLOE
SLRD
rv6
rv5
rv4
rv3
0
0
0
0
0
0
0
0
b2
b1
b0
Default Access
D2
D1
D0
xxxxxxxx RW
CLKINV
GSTATE
CLKOE
IFCFG1
8051RES 00000010 rrbbbbbr
IFCFG0 11000000 RW
FLAGA2 FLAGA1 FLAGA0 00000000 RW
FLAGC2 FLAGC1 FLAGC0 01000000 RW
EP2
EP1
EP0
xxxxxxxx W
BPPULSE
A10
A2
0
BPEN
A9
A1
230UART1
0
A8
A0
230UART0
00000000
xxxxxxxx
xxxxxxxx
00000000
rrrrbbbr
RW
RW
rrrrrrbb
SLWR
EF
FF
00000000 rrbbbbbb
rv2
rv1
rv0
Rev A, B - R
00000000
Rev C, D -
00000010
Rev E -
00000100
0
dyn_out
enh_pkt 00000000 rrrrrrbb
0
HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
ENDPOINT CONFIGURATION
E610 1 EP1OUTCFG Endpoint 1-OUT Configura- VALID
0
TYPE1
TYPE0
0
0
0
0
10100000 brbbrrrr
tion
E611 1 EP1INCFG
Endpoint 1-IN Configuration VALID
0
TYPE1
TYPE0
0
0
0
0
10100000 brbbrrrr
E612 1 EP2CFG
Endpoint 2 Configuration
VALID
DIR
TYPE1
TYPE0
SIZE
0
BUF1
BUF0 10100010 bbbbbrbb
E613 1 EP4CFG
Endpoint 4 Configuration
VALID
DIR
TYPE1
TYPE0
0
0
0
0
10100000 bbbbrrrr
E614 1 EP6CFG
Endpoint 6 Configuration
VALID
DIR
TYPE1
TYPE0
SIZE
0
BUF1
BUF0 11100010 bbbbbrbb
E615 1 EP8CFG
Endpoint 8 Configuration
VALID
DIR
TYPE1
TYPE0
0
0
0
0
11100000 bbbbrrrr
2 reserved
E618 1 EP2FIFOCFG^[6] Endpoint 2 / slave FIFO con-
0
figuration
E619 1 EP4FIFOCFG^[6] Endpoint 4 / slave FIFO con-
0
figuration
E61A 1 EP6FIFOCFG^[6] Endpoint 6 / slave FIFO con-
0
figuration
E61B 1 EP8FIFOCFG^[6] Endpoint 8 / slave FIFO con-
0
figuration
INFM1
INFM1
INFM1
INFM1
OEP1 AUTOOUT AUTOIN ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
OEP1 AUTOOUT AUTOIN ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
OEP1 AUTOOUT AUTOIN ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
OEP1 AUTOOUT AUTOIN ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
4 reserved
E620 1 EP2AUTOINLENH Endpoint 2 AUTOIN Packet
0
0
0
0
0
PL10
PL9
PL8 00000010 rrrrrbbb
[6]
Length H
E621 1 EP2AUTOINLENL Endpoint 2 AUTOIN Packet
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0 00000000 RW
[6]
Length L
E622 1 EP4AUTOINLENH Endpoint 4 AUTOIN Packet
0
0
0
0
0
0
PL9
PL8 00000010 rrrrrrbb
[6]
Length H
E623 1 EP4AUTOINLENL Endpoint 4 AUTOIN Packet
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0 00000000 RW
[6]
Length L
E624 1 EP6AUTOINLENH Endpoint 6 AUTOIN Packet
0
0
0
0
0
PL10
PL9
PL8 00000010 rrrrrbbb
[6]
Length H
E625 1 EP6AUTOINLENL Endpoint 6 AUTOIN Packet
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0 00000000 RW
[6]
Length L
E626 1 EP8AUTOINLENH Endpoint 8 AUTOIN Packet
0
0
0
0
0
0
PL9
PL8 00000010 rrrrrrbb
[6]
Length H
E627 1 EP8AUTOINLENL Endpoint 8 AUTOIN Packet
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0 00000000 RW
[6]
Length L
8 reserved
E630 1 EP2FIFOPFH^[6]
H.S.
E630 1 EP2FIFOPFH^[6]
F.S.
E631 1 EP2FIFOPFL^[6]
H.S.
Endpoint 2 / slave FIFO Pro-
grammable Flag H
Endpoint 2 / slave FIFO Pro-
grammable Flag H
Endpoint 2 / slave FIFO Pro-
grammable Flag L
DECIS
DECIS
PFC7
PKTSTAT IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]
OUT:PFC12 OUT:PFC11 OUT:PFC10
PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10
PFC6
PFC5
PFC4
PFC3
0
0
PFC2
PFC9
PFC9
PFC1
PFC8 10001000 bbbbbrbb
IN:PKTS[2] 10001000 bbbbbrbb
OUT:PFC8
PFC0 00000000 RW
Note:
6. Read and writes to these register may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”
Document #: 38-08012 Rev. *E
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