CY7C68013 Datasheet, PDF (17/48 Pages) Cypress Semiconductor – EZ-USB FX2 USB Microcontroller

CY7C68013
Table 4-1. FX2 Pin Descriptions (continued)^[5]
128 100 56 56
TQFP TQFP SSOP QFN Name
Type
35
EA
Input
12 11 12 5 XTALIN
Input
11 10 11 4 XTALOUT Output
1 100 5 54 CLKOUT
O/Z
Port A
82 67
40 33 PA0 or
INT0#
I/O/Z
83 68 41 34 PA1 or
INT1#
I/O/Z
84 69 42 35 PA2 or
SLOE
I/O/Z
85 70 43 36 PA3 or
WU2
I/O/Z
89 71 44 37 PA4 or
I/O/Z
FIFOADR0
90 72 45 38 PA5 or
I/O/Z
FIFOADR1
91 73 46 39 PA6 or
PKTEND
I/O/Z
Default
Description
N/A External Access. This pin determines where the 8051 fetches
code between addresses 0x0000 and 0x1FFF. If EA = 0 the 8051
fetches this code from its internal RAM. IF EA = 1 the 8051 fetches
this code from external memory.
N/A Crystal Input. Connect this signal to a 24-MHz parallel-resonant,
fundamental mode crystal and load capacitor to GND.
It is also correct to drive XTALIN with an external 24 MHz square
wave derived from another clock source.
N/A Crystal Output. Connect this signal to a 24-MHz parallel-
resonant, fundamental mode crystal and load capacitor to GND.
If an external clock is used to drive XTALIN, leave this pin open.
12 MHz 12-, 24- or 48-MHz clock, phase locked to the 24-MHz input clock.
The 8051 defaults to 12-MHz operation. The 8051 may tri-state
this output by setting CPUCS.1 = 1.
I
(PA0)
Multiplexed pin whose function is selected by:
PORTACFG.0
PA0 is a bidirectional IO port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which
is either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
I
(PA1)
Multiplexed pin whose function is selected by:
PORTACFG.1
PA1 is a bidirectional IO port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which
is either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
I
(PA2)
Multiplexed pin whose function is selected by two bits:
IFCONFIG[1:0].
PA2 is a bidirectional IO port pin.
SLOE is an input-only output enable with programmable polarity
(FIFOPOLAR.4) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
I
(PA3)
Multiplexed pin whose function is selected by:
WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled by WU2EN
bit (WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the
8051 is in suspend and WU2EN = 1, a transition on this pin starts
up the oscillator and interrupts the 8051 to allow it to exit the
suspend mode. Asserting this pin inhibits the chip from
suspending, if WU2EN=1.
I
(PA4)
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave FIFOs
connected to FD[7..0] or FD[15..0].
I
(PA5)
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave FIFOs
connected to FD[7..0] or FD[15..0].
I
(PA6)
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input-only packet end with programmable polarity
(FIFOPOLAR.5) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
Document #: 38-08012 Rev. *E
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