LUPA-1300 Datasheet, PDF (37/48 Pages) Cypress Semiconductor – 1.3 M Pixel High Speed CMOS Image Sensor

LUPA-1300
Datasheet
D15 104
C15 105
E13 106
D14 107
B15 108
C14 109
D13 110
B14 111
C13 112
C12 113
C11 114
B13 115
B11 116
B12 117
A15 118
C10 119
B10 120
A14 121
A13 122
A12 123
C9 124
B9 125
A11 126
A10 127
A9 128
C8 129
B8 130
A8 131
A7 132
Sample
Precharge
Eos_y
Gnd_Res
Vres
Vres_ds
Vmem_h
Vmem_l
Vddr
Vpix
Vdd
Gnd
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
Load_addr
Address
Clock_spi
Decy_load
Sync_y
Clock_y
Norow_sel
Digital I/O
Digital I/O
Digital I/O
Ground_ab
Supply
Supply
Supply
Supply
Supply 5V
Supply 5V
Supply 5V
Ground
Samples the photodiode voltage onto the
memory cell inside each pixel : active high
pulse
Precharge the memory cell inside the pixel :
active high pulse
End of scan signal of the y-register : active
high pulse indicates the end of the shift
register is reached
Ground for the reset drivers. Can be used as
anti-blooming by applying 1V instead of 0V
Voltage supply for reset drivers : 5V – 6V
(typ: 6V)
Voltage supply for reset double sloped drivers
: 4V – 5V
Voltage supply for Vmemory drivers : 5V- 6V
(typ: 6V)
Voltage supply for Vmemory drivers : 3V- 5V
(typ: 4.5V)
Supply voltage of the logic for the drivers :
5V
Supply voltage pixel array : 5V
Supply voltage digital modules : 5V
Ground of the sensor
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Loads the address into the serial parallel
interface (SPI)
Serial address to be downloaded into the SPI
Clock for the SPI
Bias for y address register : 27KΩ to ground
and capacitor of 100nF to Vdd
Synchronisation of y-address register : active
high
Clock of y-address register
Control signal for Norow_sel mode to reduce
row blanking time : active low
Cypress Semiconductor Corporation 3901 North First Street
San Jose, CA 95134 408-943-2600
Contact [e-mail] Document # : 38-05711 Rev.**( Revision 3.1) Page 37 of 48