LUPA-1300 Datasheet, PDF (29/48 Pages) Cypress Semiconductor – 1.3 M Pixel High Speed CMOS Image Sensor

LUPA-1300
Datasheet
reduce the loss of signal in the pixel and this signal must be the envelop of Precharge
and Sample. After Vmemory is high again, the readout of the pixel array can start.
The frame blanking time or frame overhead time is thus the time that Vmemory is
low, which is about 5µsec. Once the readout starts, the photodiodes can all be
initialised by reset for the next integration time. The duration of the reset pulse
indicates the integration time for the next frame. The longer this duration, the shorter
the integration time becomes. Maximum integration time is thus the time it takes to
readout the frame, minus the minimum pulse for reset, which is preferred not to be
less than 10µsec. The minimal integration time is the minimal time between the
falling edge of reset and the rising edge of sample. Keeping the slow fall times of the
corresponding internal generated signals, a minimal integration time is about 2µsec.
An additional reset pulse can be given during integration by Reset_ds to implement
the double slope integration mode. (See paragraph 6.1)
4.2 Readout of the pixel array
Once the photodiode information is stored into the memory element in each pixel, the
total pixel array of 1280 * 1024 needs to be readout in less than 2 msec (2msec –
frame overhead time = 1995µsec). Additionally, it is possible that only a part of the
whole frame is read out. This is controlled by the starting address that has to be
downloaded and from the end address, which is controlled by the synchronisation
pulses in x- and y direction. The readout itself is straightforward. Line by line is
selected by means of a sync-pulse and by means of a Clock_y signal. Once a new line
selected, it takes a while (row blanking time) before the information of that line is
stable. After this row blanking time the data is multiplexed in blocks of 16 to the
output amplifiers. A sync-pulse and a clock pulse in the x-direction do this
multiplexing.
Figure 14 shows the y-address timing. The top curves are the selection signals of the
pixels, which are sequentially active, starting by the sync pulse. The next line is
selected on the rising edge of Clock_y. It is important that the Sync_y pulse covers 1
rising edge of the Clock_y signal. Otherwise the synchronization will not work
properly.
Figure 14 : timing of the y shift register.
The first selected line after a Sync_y pulse is the line defined by the y-address in the
y-address register. Every select line is in principle 1 clock period long, except for the
Cypress Semiconductor Corporation 3901 North First Street
San Jose, CA 95134 408-943-2600
Contact [e-mail] Document # : 38-05711 Rev.**( Revision 3.1) Page 29 of 48