CY8C21345AUTO Datasheet, PDF (3/36 Pages) Cypress Semiconductor – Automotive PSoC® Programmable System-on-Chip™

CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
PSoC Functional Overview
The PSoC programmable system-on-chip series of products
consists of many devices. These devices are designed to
replace multiple traditional MCU-based system components with
one low cost single-chip programmable device. PSoC devices
include configurable blocks of analog and digital logic, as well as
programmable interconnects. This architecture enables the user
to create customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, flash program memory, SRAM data memory, and
configurable I/O are included in a range of convenient pinouts
and packages.
The PSoC architecture, shown in the Block Diagram on page 1,
consists of four main areas: PSoC core, digital system, analog
system, and system resources. Configurable global busing
allows the combining of all the device resources into a complete
custom system. The PSoC family can have up to five I/O ports
connecting to the global digital and analog interconnects,
providing access to eight digital blocks^[1] and six analog blocks.
PSoC Core
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO.
The M8C CPU core is a powerful processor with speeds up to
24 MHz (up to 12 MHz for E-grade devices), providing four MIPS
(two MIPS for E-grade devices) 8-bit Harvard architecture micro-
processor. The CPU uses an interrupt controller to simplify the
programming of real time embedded events.
Program execution is timed and protected using the included
Sleep Timer and Watch Dog Timer (WDT).
Memory encompasses 16 KB of flash (8 KB for CY8C21x45
devices) for program storage, 1 KB of SRAM (512 bytes for
CY8C21x45 devices) for data storage, and EEPROM emulation
using the flash. Program flash uses four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
The PSoC device incorporates flexible internal clock generators,
including a 24-MHz internal main oscillator (IMO). For A-grade
devices the 24-MHz IMO can also be doubled to 48 MHz for use
by the digital system. A low-power 32-kHz internal low-speed
oscillator (ILO) is provided for the Sleep Timer and WDT. If
crystal accuracy is required, the 32.768 kHz external crystal
oscillator (ECO) is available for use as a RTC, and can optionally
generate a crystal-accurate 24-MHz system clock using a PLL.
The clocks, together with programmable clock dividers (as a
system resource), provide the flexibility to integrate almost any
timing requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital, and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Each pin can also generate a system interrupt.
Digital System
The digital system is composed of eight digital PSoC blocks.
Each block is an 8-bit resource that may be used alone or
combined with other blocks to form 8-, 16-, 24-, and 32-bit
peripherals, which are called user modules.
Figure 1. Digital System Block Diagram^[1]
Port 4
Port 3
Port 2
Port 1
Port 0
8
8
Digital Clocks ^{To System Bus}
From Core
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row 0
4
DBC00 DBC01 DCC02 DCC03
4
Row 1
DBC00 DBC01 DCC02 DCC03
8
8
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital peripheral configurations are:
■ PWMs (8- to 32-bit)
■ PWMs with deadband (8- to 32-bit)
■ Counters (8- to 32-bit)
■ Timers (8- to 32-bit)
■ One-shot and multi-shot modules
■ Full or half-duplex 8-bit UART with selectable parity (up to two
full-duplex or four half-duplex)
■ SPI master and slave (up to four total) with programmable data
length from 8 to 16 bits.
■ Shift register (1- to 32-bit)
■ I²C master, slave, or multi-master (one available)
■ CRC/generator (16-bit)
■ IrDA (up to two)
■ PRS generators (8- to 32-bit)
Note
1. CY8C22x45 devices have 2 digital rows with 8 digital blocks. CY8C21x45 devices only have 1 digital row with 4 digital blocks.
Document Number: 001-55397 Rev. *I
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