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CY8C21345AUTO Datasheet, PDF (1/36 Pages) Cypress Semiconductor – Automotive PSoC® Programmable System-on-Chip™ | |||
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CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
Automotive PSoC®
Programmable System-on-Chipâ¢
Features
â Automotive Electronics Council (AEC) Q100 qualified
â Powerful Harvard-architecture processor
â M8C processor speeds up to 24 MHz
â 8 Ã 8 multiply, 32-bit accumulate
â Low power at high speed
â Automotive A-grade: 3.0 V to 5.25 V operation at â40 °C to
+85 °C temperature range
â Automotive E-grade: 4.75 V to 5.25 V operation at â40 °C to
+125 °C temperature range
â Advanced peripherals (PSoC® blocks)
â Six analog Type âEâ PSoC blocks provide:
⢠Up to four comparators with digital-to-analog converters
(DAC) references
⢠Up to 10-bit single or dual analog-to-digital converters
(ADCs)
â Up to eight digital PSoC blocks provide:
⢠8 to 32-bit timers, counters, and pulse width modulators
(PWMs)
⢠One-shot, multi-shot mode in timers and PWMs
⢠PWM with deadband in one digital block
⢠Shift register, cyclical redundancy check (CRC), and
pseudo random sequence (PRS) modules
⢠Full- or half-duplex UARTs
⢠SPI masters or slaves, 8- to 16-bit variable data length
⢠Connectable to all general-purpose I/O (GPIO) pins
â Complex peripherals by combining blocks
â Powerful synchronization support, analog module operations
can be synchronized by digital blocks or external signals.
â High-speed 10-bit successive approximation register (SAR)
ADC with sample and hold optimized for embedded control
â CY8C22345H devices integrate Immersion® TouchSense®
haptics technology for ERM drive control
â Precision, programmable clocking
â Internal oscillator up to 24 MHz
â High accuracy 24 MHz with optional 32-kHz crystal and
phase locked loop (PLL)
â Optional external oscillator, up to 24 MHz
â Internal low speed, low-power oscillator for watchdog and
sleep functionality
â Flexible on-chip memory
â Up to 16 KB flash program storage, 1000 erase/write cycles
â Up to 1 KB SRAM data storage
â In-System Serial Programming (ISSP)
â Partial flash updates
â Flexible protection modes
â EEPROM emulation in flash
â Optimized CapSense® resource
â Supports two CapSense channels with simultaneous
scanning
â Two current DACs provide programmable sensor tuning in
firmware
â Two dedicated clock resources for CapSense
â Two dedicated 16-bit timers/counters for CapSense
scanning
â Versatile analog mux
â Common internal analog bus
â Simultaneous connection of I/O combinations
â Programmable pin configurations
â 25 mA sink, 10 mA drive on all GPIOs
â Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIOs
â Analog input on all GPIOs
â Configurable interrupt on all GPIOs
â Additional system resources:
â I2C master, slave, or multi-master
⢠Operation up to 400 kHz
⢠Hardware address detection feature
â Watchdog and sleep timers
â User-configurable low voltage detection
â Integrated supervisory circuit
â On-chip precision voltage reference
â Hardware real time clock (RTC) block
Block Diagram
PSoC CORE
Port 4 Port 3 Port 2 Port 1 Port 0
System Bus
Global Digital
Interconnect
SRAM
1KB/512B
Interrupt
Controller
Global Analog Interconnect
SROM Flash 16K/8K
CPU Core (M8C)
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital Block
Array
CapSense Digital
Resources
ANALOG SYSTEM
10-bit SAR
ADC
Analog
Block
Array
Analog
Ref
Analog
Input
Muxing
Digital
Clocks
Multiply
Accum.
I2C
RTC
POR and LVD
System Resets
SYSTEM RESOURCES
Internal
Voltage
Ref.
Cypress Semiconductor Corporation ⢠198 Champion Court
Document Number: 001-55397 Rev. *I
⢠San Jose, CA 95134-1709 ⢠408-943-2600
Revised March 18, 2011
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