CY7C924ADX Datasheet, PDF (25/56 Pages) Cypress Semiconductor – 200-MBaud HOTLink Transceiver

CY7C924ADX
Capacitance^[8]
Parameter
C_INTTL
C_INPECL
Description
TTL Input Capacitance
PECL-compatible input Capacitance
Test Conditions
T_A = 25°C, f₀ = 1 MHz, V_DD = 5.0V
T_A = 25°C, f₀ = 1 MHz, V_DD = 5.0V
AC Test Loads and Waveforms
Max.
Unit
7
pF
4
pF
5.0V
OUTPUT
R1
R1 = 500 Ω
R2 = 333 Ω
C_L ≤ 10 pF
(Includes fixture and
probe capacitance)
C_L
R2
(a) TTL AC Test Load^[9]
3.0V
V_th=1.5V
0.0V
≤ 1 ns
2.0V
0.8V
3.0V
2.0V
0.8V
Note 9
V_th=1.5V
≤ 1 ns
V_DD – 1.33V
C_L
R_L
R_L = 50 Ω
C_L < 5 pF
(Includes fixture and
probe capacitance)
(b) PECL AC Test Load ^[9]
V_{I H E}
V_ILE
20%
≤ 1 ns
80%
V_IHE
80%
V_ILE
20%
≤ 1 ns
(c) TTL Input Test Waveform
(d) PECL Input Test Waveform
CY7C924ADX Transmitter TTL Switching Characteristics, FIFO Enabled Over the Operating Range
Parameter
Description
f_TS
TXCLK Clock Cycle Frequency With Transmit FIFO Enabled
t_TXCLK
TXCLK Period
t_TXCPWH
TXCLK HIGH Time
t_TXCPWL
t_TXCLKR ^[8]
t_TXCLKF ^[8]
TXCLK LOW Time
TXCLK Rise Time^[10]
TXCLK Fall Time^[10]
t_TXA
Flag Access Time From TXCLK↑ to Output
t_TXDS
Transmit Data Set-Up Time to TXCLK ↑
t_TXDH
Transmit Data Hold Time from TXCLK↑
t_TXENS
Transmit Enable Set-Up Time to TXCLK ↑
t_TXENH
Transmit Enable Hold Time from TXCLK↑
t_TXRSS
Transmit FIFO Reset (TXRST*) Set-Up Time to TXCLK↑
t_TXRSH
Transmit FIFO Reset (TXRST*) Hold Time from TXCLK↑
t_TXAMS
Transmit Address Match (AM*) Set-Up Time to TXCLK↑
t_TXAMH
Transmit Address Match (AM*) Hold Time from TXCLK↑
t_TXZA
Sample of AM* LOW by TXCLK↑, Output High-Z to Active HIGH or LOW
t_TXOE
Sample of AM* LOW by TXCLK↑ to Output Valid
t_TXAZ
Sample of AM* HIGH by TXCLK↑ to Output in High-Z
Notes:
8. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
9. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
10. Input/output rise and fall time is measured between 0.8V and 2.0V .
Min.
20
6.5
6.5
0.7
0.7
2
4
1
4
1
4
1
4
1
0
1.5
1.5
Max.
50
5
5
15
20
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-02008 Rev. *D
Page 25 of 56