CY7C924ADX Datasheet, PDF (22/56 Pages) Cypress Semiconductor – 200-MBaud HOTLink Transceiver

CY7C924ADX
characters are received, all of them are discarded except the
last one received before any other character type. This allows
these fill characters to be removed from the data stream, but
does not change the data flow for protocols (like Fibre
Channel) that use a single C5.0 character as a delimiter.
Policy 2 is identical to policy 1 except that all C5.0 characters
are removed from the data stream.
Policy 3 is a super-set of policy 2, where the serial address is
also discarded.
When the FIFOs are bypassed (FIFOBYP* LOW), no
characters are actually discarded, but the receiver discard
policy can be used to control external filtering of the data. The
RXEMPTY* FIFO flag is used to indicate if the character on
the output bus is valid or not. In discard policy 0, the
RXEMPTY* flag is always deasserted to indicate that valid
data is always present. In discard policy 1 when a series of
C5.0 characters are received, the RXEMPTY* flag indicates
an empty condition for all but the last C5.0 character before
any other character is presented. In discard policies 2 or 3, the
RXEMPTY* flag indicates an empty condition for all C5.0
characters. When any other character is present, this flag
indicates that valid or “interesting” Data or Special Characters
are present.
Receive FIFO
The Receive FIFO is used to buffer data captured from the
selected serial stream for later processing by the host system.
This FIFO is sized to hold 256, 14-bit characters. When the
FIFO is enabled, it is written to by the Receive Control State
Machine. When data is present in the Receive FIFO (as
indicated by the RXFULL*, RXHALF*, and RXEMPTY*
Receive FIFO status flags), it can be read from the Output
Register by asserting AM* and RXEN*.).
The read port on the Receive FIFO may be configured for the
same two timing models as the transmit interface: UTOPIA
and Cascade. Both are forms of a FIFO interface. The
UTOPIA timing model (EXTFIFO = L) has active LOW
RXEMPTY* and RXFULL* status flags, and an active LOW
RXEN* enable. When configured for Cascade operation
(EXTFIFO = H), these same signals are all active HIGH. The
RXHALF* signal is always active LOW, regardless of
EXTFIFO setting. Either timing model supports connection to
various host bus interfaces, state machines, or external FIFOs
for depth expansion (see Figure5
EF*
REN*
Q
CY7C42x5 FIFO
EF*
FF*
REN* WEN*
Q
D
CY7C924ADX
RXEN
RXEMPTY
RXDATA
RXSC/D*
RXCLK _{RCLK WCLK}
RXCLK
“1” _EXTFIFO
Figure 5.External FIFO Depth Expansion of the
CY7C924ADX Receive Data Path
The Receive FIFO presents Full, Half-Full, and Empty FIFO
status flags. These flags are provided synchronous to RXCLK
to allow operation with a Moore-type external controlling state
machine. When configured with the Receive FIFO enabled,
RXCLK is an input. When the Receive FIFO is bypassed
(FIFOBYP* is LOW), RXCLK is an output operating at the
received character rate.
Receive Input Register
The input register is clocked by the rising edge of RXCLK. It
samples numerous signals that control the reading of the
Receive FIFO and operation of the Receive Control State
Machine.
Receive Output Register
The Receive Output Register changes in response to the
rising edge of RXCLK. When the Receive FIFO is enabled
(FIFOBYP* = H), the FIFO status flag outputs of this register
are placed in a High-Z state when the CY7C924ADX is not
addressed (AM* is sampled HIGH). The RXDATA bus output
drivers are enabled when the device is selected by RXEN*
being asserted in the RXCLK cycle immediately following that
in which the device was addressed (AM* is sampled LOW),
and RXEN* being sampled by RXCLK. This initiates a Receive
FIFO read cycle.
Just as with the TXDATA bus on the Transmit Input Register,
the receive outputs are also mapped by the specific decoding
and bus-width selected by the ENCBYP*, BYTE8/10* and
FIFOBYP* inputs. These assignments are shown in Table8.
When the Decoder and Receive FIFO are both enabled, the
Receive Control State Machine interprets and discards
(except in discard policy 0) received C0.0 and C3.0 command
codes as set and clear directives for the RXINT output. This
allows the RXINT output to duplicate the state transitions
presented to the TXINT input at the source end of the link. This
RXINT output can be used, along with TXHALT*, TXINT, and
RXHALF*, to implement a back-pressure mechanism for the
Receive FIFO, or for other time dependent signalling.
If the Receive FIFO and Decoder are bypassed, all received
characters are passed directly to the Receive Output Register.
If framing is enabled, and K28.5 characters have been
detected meeting the present framing requirements, the
output characters will appear on proper character boundaries.
If framing is disabled (RFEN is LOW) or K28.5 characters have
not been detected in the data stream, the received characters
may not be output on their proper 10-bit boundaries. In this
mode, some form of external framing and decoding/descram-
bling must be used to recover the original source data.
Serial Address Register
When the device is in Utopia mode (EXTFIFO = LOW), the
receiver is capable of selectively accepting or discarding
received data based on an address received in the data
stream. The address matching capability allows for the choice
of matching of either domains (multicast) or exact addresses
(unicast). The 8- or 10-bit Serial Address Register represents
a single character address field as shown in Figure6.
The multicast mode is bit-specific and allows allocation of up
to 8 or 10 separate domains. In the unicast address mode the
match is character specific and identifies up to 256 or 1024
destination addresses. A device can either belong to one or
more domains, or it can have a single unique address.
Document #: 38-02008 Rev. *D
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