CY7C924ADX Datasheet, PDF (10/56 Pages) Cypress Semiconductor – 200-MBaud HOTLink Transceiver

CY7C924ADX
Pin Descriptions (continued)
CY7C924ADX HOTLink Transceiver
Pin #
Name
I/O Characteristics
Signal Description
27
ENCBYP*
Static control input Encoder Bypass Select. When LOW, both the Encoder and Decoder are
TTL levels Normally bypassed. Data is transmitted in NRZ format, without encoding, LSB first.
wired HIGH or LOW Received data are presented as parallel characters to the interface without
decoding.
When HIGH, data is passed through both the 8B/10B Encoder in the Transmit
path and the Decoder in the Receive path.
24, 25 RXMODE[1:0] Static control input Receive Discard Policy Select . These inputs select between the four data
TTL levels Normally handling and fill-character discard modes in the receiver. See Table7.
wired HIGH or LOW
50
BYTE8/10*
Static control input Parallel Data Character Size Select. Selects the input data character width.
TTL levels Normally When BYTE8/10* is HIGH and ENCBYP* is HIGH, the device is in 8-bit mode
wired HIGH or LOW and the data is encoded using the 8B/10B code rules found in Table11 and
Table12. When BYTE8/10* is HIGH and ENCBYP* is LOW, the 10 parallel
data bits are passed directly to or from the serial stream without encoding or
decoding.
When BYTE8/10* is LOW, the part is in 10-bit mode. If the encoder is enabled
(ENCBYP* is HIGH) , the part passes the 10 parallel bits to the byte stuffer and
encoder. When the encoder is disabled (ENCBYP* is LOW), the 12 parallel
data bits are passed directly to or from the serial stream without encoding or
decoding.
For affected pin groupings and function see T a b l e 1 and Table8.
If the FIFOs are BYPASSED and Encoding is enabled (FIFOBYP* = LOW and
ENCBYP* = HIGH), BYTE8/10* MUST BE HIGH
52, 51 RESET*[1:0] TTL input,
Global Logic Reset . These inputs are pulsed LOW for one or more REFCLK
periods to reset the internal logic. They must be tied together or driven concur-
rently to ensure a valid reset.
1
TEST*
TTL input,
Factory Test Mode Select . Used to force the part into a diagnostic test mode
asynchronous.
used for factory ATE test. This pin is tied HIGH during normal operation.
Normally wired HIGH
Analog I/O and Control
89, 90, OUTA±
81, 82 OUTB±
97
CURSETA
PECL-compatible
differential outputs
Analog input
Differential Serial Data Outputs. These PECL-compatible outputs are
capable of driving terminated transmission lines or commercial fiber-optic
transmitter modules. An unused output pair may be powered down by leaving
the outputs unconnected and strapping the associated CURSETx pin to V_DD.
Current-set Resistor Input for OUTA±. A precision resistor is connected
between this input and a clean ground to set the output differential amplitude
and currents for the OUTA± differential driver.
78
CURSETB
Analog input
Current-set Resistor Input for OUTB±. A precision resistor is connected
between this input and a clean ground to set the output differential amplitude
and currents for the OUTB± differential driver.
94, 93, INA±
86, 85 INB±
PECL-compatible
differential inputs
Differential Serial Data Inputs. These inputs accept the serial data stream
for deserialization and decoding. Only one serial stream at a time may be fed
to the receiver PLL to extract the data content. This stream is selected using
the A/B* input. These inputs may also be routed to the OUTB± serial outputs
using the DLB[1:0] inputs.
2
A/B*
TTL input,
asynchronous,
Internal Pull-Up
Receive Data Input Selector. Determines which external serial bit-stream is
passed to the receiver clock and data recovery circuit.
4,5
DLB[1:0]
TTL input,
asynchronous,
Internal Pull-Down
Loop-back Select Inputs. Selects connections between serial inputs and
outputs. Controls diagnostic loop-back and serial loop-through functions. See
Table3for details.
Document #: 38-02008 Rev. *D
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