CY7C924ADX Datasheet, PDF (21/56 Pages) Cypress Semiconductor – 200-MBaud HOTLink Transceiver

CY7C924ADX
configurations with one or more data sources and multiple
data destinations.
Each CY7C924ADX contains an 8-bit or 10-bit Serial Address
Register that is compared with the first data character received
following a Serial Address marker (C10.0). This character
constitutes an address, which can be configured for one of two
modes for address matching. The first mode is used for
multicast addresses, where a bit-wise AND is performed on
each bit of the address character received, with the contents
of each of the bits in the Serial Address Register. If any of the
same bit locations in the register and the received data are
both set to ‘1’, a multicast address match is declared and the
following data and Special Character codes are interpreted
and passed to the Receive FIFO.
If the multicast address field is ever received as all 1s (FFh or
3FFh), the receiver always accepts the data. This all 1s setting
is the broadcast address and is used to send data to all
receivers.
This all 1s setting also has special meaning when written to
the Serial Address Register. When the multicast address field
is written to an all 1s (FFh or 3FFh) state, the receiver operates
in promiscuous mode, and receives all data, regardless of the
contents of any serial address commands received. This is
also the default or power-up state of the Serial Address
register.
The second mode of operation for address matching is when
the Serial Address register contains a unique device address,
and is compared with the character received following the
C10.0 Serial Address marker. This unicast address requires
an exact match between all 8 or 10 bits to declare a match
found and allow the following data to pass.
When the Elasticity Buffer is enabled, all received characters
(except C5.0) are written to the Elasticity Buffer, regardless of
the state or configuration of any present address match. This
allows one or more sources to send data to multiple receivers
with the receivers connected in a ring or daisy-chain topology.
By prefacing cells containing data with an address field, it is
possible to have each receiver only process data specifically
directed to it.
Byte-Unpacker
The Byte-Unpacker is used to re-assemble 10-bit characters
from a received stream of decoded 8-bit characters. This
reassembly process is designed to allow transmission of the
same embedded commands, serial addresses, and Start of
Cell markers that are used with 8-bit data characters. Because
of the change in time per received encoded character versus
delivered 10-bit data character, this unpacking process is only
possible with the Receive FIFO enabled.
The byte-unpacker reverses the character segmentation
shown in Figure 4. It takes five data characters and combines
them into four 10-bit characters. This five-state unpacking
process is re-started by the detection of any Special Character
code in the Decoder, including the C5.0 (K28.5) fill character.
Since usage of the Elasticity Buffer inserts and deletes C5.0
characters (as necessary) to handle the speed differences
between the receive and transmit character clocks, it is not
possible to send byte-packed data through the Elasticity
Buffer. To send 10-bit packed data from one source to multiple
destinations it is necessary to either use a star topology of
interconnect, or make use of the buffered and reclocked serial
input-to-output connections controlled by the Routing Matrix.
Receive Control State Machine
The Receive Control State Machine responds to multiple input
conditions to control the routing and handling of received
characters. It controls the staging of characters across various
registers and the Receive FIFO. It also interprets all
embedded Special Character codes, and converts the appro-
priate ones to specific bit combinations in the Receive FIFO.
It controls the various discard policies and error control within
the receiver, and operates in response to:
• the received character stream
• the detection and validation of serial addresses
• the room for additional data in the Receive FIFO
• the state of the receiver BIST enable (RXBISTEN*)
• the state of LOOPTX
• the state of FIFOBYP*.
These signals and conditions are used by the Receive Control
State Machine to control the Receive Formatter, write access
to the Receive FIFO, write access to the Elasticity Buffer, the
Byte-Unpacker, the Receive Output register, and BIST. They
determine the content of the characters passed to each of
these destinations,
The Receive Control State Machine always operates
synchronous to the recovered character clock (bit-clock/10 or
bit-clock/12). When the Receive FIFO is bypassed, RXCLK
becomes an output that changes synchronous to the internal
character clock. RXCLK operates at the same frequency as
the internal character clock.
Discard Policies
When the Receive FIFO is enabled, the Receive Control State
Machine has the ability to selectively discard specific
characters from the data stream that are determined by the
present configuration as being unnecessary. When discarding
is enabled, it reduces the host system overhead necessary to
keep the Receive FIFO from overflowing and losing data.
The discard policy is configured as part of the operating mode
and is set using the RXMODE[1:0] inputs. The four discard
policies are listed in Table7.
Table 7. Receiver Discard Policies
Policy # RXMODE[1:0] Policy Description
0
00
Keep all received characters
1
01
Process Commands, discard all
but the last C5.0 character
2
10
Process Commands, discard all
C5.0 characters
3
11
Process Commands, discard all
C5.0 characters, discard serial
addresses
Policy 0 is the simplest and also applies for all conditions
where the Receive FIFO is bypassed. In this mode, every
character that is received is placed into the Receive FIFO
(when enabled) or into the Receive Output Register.
In discard policy 1, all Start Of Cell, extended command, and
serial address commands are processed as they are received.
The C5.0 character, which is automatically transmitted when
no data is present in the Transmit FIFO, is treated differently
here. In this mode, whenever two or more adjacent C5.0
Document #: 38-02008 Rev. *D
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