CY7C924ADX Datasheet, PDF (2/56 Pages) Cypress Semiconductor – 200-MBaud HOTLink Transceiver

CY7C924ADX
CY7C924ADX Transceiver Logic Block Diagram
TX
STATUS
TXDATA CONTROL TXCLK
MODE _REFCLK
11 ₉
13
3
RX
STATUS
4
RXDATA
13
Output Register
Mode
Control
Output Register
RXCLK
Address Register
Input Register
Flags
MUX
Flags
Transmit
FIFO
MUX
Transmit
Formatter
Pipeline Register
Byte-Packer
BIST LFSR
8B/10B Encoder
MUX
Serial Shifter
LOOPBACK
CONTROL
DLB[1:0]
LOOPTX
3
Transmit
PLL Clock
Multiplier
Elasticity
Buffer
Receive
FIFO
MUX
Receive
Formatter
Pipeline Register
Byte-Unpacker
Address Matching
Receive
Control
State
Machine
BIST LFSR
8B/10B Decoder
Transmit
Control
State
Machine
Bit Clock
Deserializer
Framer
Clock
Divider
Receive
Clock/Data
Recovery
Bit Clock
Routing Matrix
Mode
CONTROL
AM*
TXEN*
RXEN*
TXSTOP*
TXRST*
RXRST*
RFEN
TXBISTEN*
RXBISTEN*
RESET*[1:0]
MODE
RANGESEL
SPDSEL
RXMODE[1:0]
FIFOBYP*
EXTFIFO
ENCBYP*
BYTE8/10*
TEST*
RXSTATUS
LFI*
RXEMPTY*
RXHALF*
RXFULL*
TX STATUS
TXEMPTY*
TXHALF*
TXFULL*
Signal
Validation
LOOPBACK
CONTROL
OUTA
CURSETA
OUTBCURSETB
INA
INB A/B*
CARDET
Document #: 38-02008 Rev. *D
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