IBIS4-1300 Datasheet, PDF (11/37 Pages) Cypress Semiconductor – 1.3 MPxl Rolling Shutter CMOS Image Sensor

IBIS4-1300
Table 2. Pins of the image sensor core
Digital controls
GND_AB
54
Power & ground
VDD_RESETL
59
VDD_RESETR
79
VDD_ARRAY
55
VDD
11
34
53
77
GND
10
33
52
78
Anti-blooming drain control voltage
• Default: connect to ground. The anti blooming is operational but
not maximal.
• Apply about 1 V DC for improved anti-blooming
Power supply for left reset line drivers apply 5 V DC (default) or about
4…4.5 V for dual slope mode
Power supply for right (default) reset line drivers 5 V DC
Power supply for the pixel array 5 V DC
Power supply of image sensor core & output amplifier 5 V DC
Ground of image sensor core & output amplifier
Output amplifier
The output amplifier stage is user-programmable for gain and
offset level. Gain and offset are controlled by 4-bit wide words.
Gain settings are on an exponential scale. Offset is controlled
by a 4-bit wide DAC, which selects the offset voltage between
2 reference voltages (Vhigh_dac & Vlow_dac) on a linear
scale.
Table 3. Summary of output amplifier specifications
Min.
Gain
1.2 (gain setting 0)
Output signal range
1V
Bandwidth
(40 pF load)
12 MHz
(gain setting 15)
Output slew rate
(40 pF load)
40 V/ µs
The offset setting is independent of the gain setting.
The gain setting is independent of amplifier bandwidth.
The amplifier is designed to match the specifications like the
output of the imager array. This signal has a data rate of 10
MHz and is located between 1.2 and 2.4 V. Table 3.
summarizes the specifications of the amplifier.
Typ
2.7 (setting 4)
22 MHz
(gain setting 0...8)
50 V/µs
Max
16 (setting 15)
4.5 V
33 MHz
(gain setting 0)
80 V/µs
The range of the output stage input is between 1 and 4 V. A
lowest gain the sensor outputs a signal in between 1.2 and 2.2
V, which fits into the input range of the amplifier. The range of
the output signal is between 1 and 4.5 V, dependent on the
gain and offset settings of the amplifier. This range should fit
to the input range of the ADC, external or internal. The
on-chip ADC range is between 2 and 4 V. A minimal gain
setting of "3" seems necessary for the internal ADC, and the
offset voltage should be set to the low-reference voltage of the
ADC.
Document Number: 38-05707 Rev. *B
Page 11 of 37
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