IBIS4-1300 Datasheet, PDF (10/37 Pages) Cypress Semiconductor – 1.3 MPxl Rolling Shutter CMOS Image Sensor

IBIS4-1300
Figure 5. shows the pixel response curve in linear response
mode. This curve is the relation between the electrons
detected in the pixel and the output signal. This curve was
measured with light of 600 nm, with an integration time of
138.75 ms (10 MHz pixel rate), at minimal gain setting 0000.
The resulting voltage/electron curve is independent of these
parameters. The conversion gain is 18 uV/electron for this gain
setting.
Note that the upper part of the curve (near saturation) is
actually a logarithmic response, similar to the FUGA1000
sensor. The level of saturation can be adjusted by the voltage
on GND-AB. However note also that this logarithmic part of the
response is not FPN corrected by the on-chip offset correction
circuitry.
The signal swing (and thus the dynamic range) is extended by
increasing the VDD_RESET (pins 59/79) to 5.5 V. This is
mode of operation is not further documented.
Table 2. shows the pins of the IC that are related to the image
sensor core, describing their functionality.
Table 2. Pins of the image sensor core
Digital controls
SYNC_YR\
5
Reset right Y shift register (low active, 0 = sync)
CLK_YR
6
Clock right Y shift register (shifts on falling edge)
EOS_YR\
7
(output) low 1st CLK_YR pulse after last row (low active)
SYNC_X\
28
Reset X shift register (low active, 0 = sync)
CLK_X
29
Clock X shift register (shifts on falling edge)
EOS_X\
8
(output) Low 1st CLK_X pulse after last active column (low active)
SYNC_YL\
36
Reset left Y shift register (low active, 0 = sync)
CLK_YL
37
Clock left Y shift register (shifts on falling edge)
EOS_YL\
38
Low 1st CLK_YL pulse after last row
SHY
30
Parallel Y track & hold (1 = hold, 0 = track) apply pulse pattern - see
sensor timing diagram
SIN
35
Column amplifier calibration pulse
1 = calibrate - see sensor timing diagram
SELECT
40
Selects row indicated by left/right shift register high active (1= select
row)
Apply 5 V DC for normal operation
RESET
41
Resets row indicated by left/right shift register high active (1 = reset)
Apply pulse pattern - see timing diagram
L/R\
80
Use left or right register for SELECT and RESET
1 = left / 0 = right - see sensor timing
SUBSMPL
84
Activate viewfinder mode (1:4 sub sampling = 320 x 256 pixels) high
active, 1 = sub sampling
Reference voltages
DCCON
31
Control voltage for the DCREF voltage generation Connect to ground
by default
DCREF
32
Reference voltage (output), to be decoupled to GND
Should be about 1.2V, can be adjusted by DCCON
NBIASARRAY
1
1 MegaOhm to VDD and decouple to ground by 100 nF capacitor
PBIAS2
2
1 MegaOhm to ground and decouple to VDD by 100 nF capacitor
PBIAS
3
1 MegaOhm to ground and decouple to VDD by 100 nF capacitor
XMUX_NBIAS
4
100K to VDD and decouple to ground by 100 nF capacitor
Document Number: 38-05707 Rev. *B
Page 10 of 37
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