STAR1000_09 Datasheet, PDF (10/21 Pages) Cypress Semiconductor – 1M Pixel Radiation Hard CMOS Image Sensor

STAR1000
Table 6. Timing Constraints of Line Sequence
Symbol
Min
Typ
Description
e
1.6 μs
Delay between falling edge of reset and falling edge of R.
f
0
100 ns
Minimum delay between falling edge on LD_Y and rising edge of reset.
g
g
Minimum required extension of Y- address after falling edge of reset pulse.
h
100 ns
200 ns
Position of cal pulse after rising edge of S.
The cal pulse must only be given once per frame.
i
100 ns
1 μs
Duration of cal pulse.
k
10 ns
Address set up time.
l
20 ns
Load register value.
m
10 ns
Address stable after load.
Pixel Read Out Timing
Figure 6 on page 11 shows the timing of the pixel readout
sequence. The external digital controller presents a column
address that is latched by the rising edge of the LD_X pulse. After
decoding the X- address the column selection is clocked in the
X- register by CLK-X. The output amplifier uses the same pulse
to subtract the pixel output level from the pixel reset level and the
signal level. This causes a pipeline effect such that the analog
output of the first pixel is effectively present at the device output
terminal at the third rising edge of the X-CLK signal.
The ADC conversion starts at the falling edge of the CLK-ADC
signal and produces a valid digital output 20 ns after this edge.
The timing constraints are given in Table 7 on page 11
Important note: The values of the X shift-register tend to leak
away after a while. Therefore, it is very important to keep the
CLK_X signal asserted for as long as the sensor is powered up.
If the sensor sits idle and CLK_X is not asserted, the leakage of
the X shift-register causeq multiple columns to be selected at
once. This forces high current through the sensor and may cause
damage.
Document Number: 38-05714 Rev. *C
Page 10 of 21
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