STC3800 Datasheet, PDF (5/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3E TIMING SOURCE

Pin Name
Sel0
Sel1
Sel2
Sel3
BITS_Sel
LOS
LOL
Hold_Avail
Xref
Ref1
Ref2
Ref3
Ref4
Ref5
Ref6
Ref7
Ref8
Sync_Clk
Sync_8K
BITS_Clk
Sync_2K
M_Clk
VC_TTL
VC_PPECL
VC_NPECL
VC_Sel
DACclk
DACdin
DACld
E²scl
E²sda
E²wp
MNC
Pin #
A9
A10
A11
A12
C11
H2
J2
K2
K1
M1
M2
M3
M4
M5
M6
M7
M8
G12
J12
L11
K12
F1
F12
F11
E11
D11
B12
C12
D12
D1
D2
E2
G1, G4,
L10,
M11, M12
Pin Description
Table 1 continued
I/O
Description
I
In Hardware Mode (HM_Ref = 1), Sel0 ~ Sel3 will determine the Free Run,
Locked, Hold Over, and the Active Reference in Locked Mode.
See Table 5 in Hardware Control Modes section
I
See Table 5 in Hardware Control Modes section
I
See Table 5 in Hardware Control Modes section
I
See Table 5 in Hardware Control Modes section
I
1.544 MHz or 2.048 MHz BITS clock selection, 1 = 1.544 MHz, 0 = 2.048 MHz
O
Loss of signal indicator for the selected reference, 1 = Loss of Signal
O
Loss of phase lock, 1 = Loss of Lock
O
Hold Over history built and usable = 1
I
Cross Reference Input
I
Reference Input 1
I
Reference Input 2
I
Reference Input 3
I
Reference Input 4
I
Reference Input 5
I
Reference Input 6
I
Reference Input 7
I
Reference Input 8
O
Synchronous Clock: Output frequency is dependent on VCXO frequency
O
Synchronous Clock: 8 kHz
O
BITS clock output
O
Multi-frame sync: 2 kHz
I
OCXO or TCXO local crystal oscillator input
I
VCXO TTL input
I
VCXO PPECL input
I
VCXO NPECL input
I
Selects the input VCXO signal electrical format, 0: PECL, 1: TTL
O
DAC Serial Bus Interface: CLK
O
DAC Serial Bus Interface: Din
O
DAC Serial Bus Interface: CS/LD
O
EEPROM interface: SCL
I/O
EEPROM interface: SDA
O
EEPROM interface: WP
Mandatory no-connect - must be left floating
Preliminary Data Sheet #: TM061 Page 5 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice