STC3800 Datasheet, PDF (16/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3E TIMING SOURCE

Detailed Description continued
Output Signals and Frequency
Sync_Clk is the primary chip output, and in locked mode is synchronized to the selected reference. Sync_Clk is a
buffered version of the VC_TTL input from VCXO, thus the output frequency is exactly the same as the VCXO
frequency. The VCXO may be any of the following frequencies: 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz,
51.84 MHz, or 77.76 MHz See External Component Selection section. Operation at 155.52 MHz is also permitted
with a 155.52 MHz VCXO, and requires a PECL buffer to provide the main clock output. (See Application Notes/
Peripherals section). Device PECL VCXO clock input also needs to be selected (via the VC_Sel pin). When PECL
outputs are selected, the Sync_Clk output is disabled.
Sync_8K is an 8 kHz output available as a frame reference or may be used as a synchronization signal for cross-
coupled pairs of STC3800 devices operated in master/slave mode. Sync_8K may be a 50% duty cycle signal, or
variable high-going pulse width, as determined by the Ctl_Mode and Fr_Pulse_Width registers. In variable pulse width
mode, the width may be from 1 to 15 multiples of the Sync_Clk cycle time. See Register Descriptions and Operation
section.
Sync_2K is a 2 kHz multi-frame sync output. It may be a 50% duty cycle signal, or variable high-going pulse width, as
determined by the Ctl_Mode and Fr_Pulse_Width registers. In variable pulse width mode, the width may be from 1 to
15 multiples of the Sync_Clk cycle time. See Register Descriptions and Operation section.
These three output signals are phase aligned, and in locked mode are synchronized to the selected reference. In slave
mode, they are in phase with the Xref input, offset by the value written to the MS_Phase_Offset register (+31.75 to -
32nS, with .25nS resolution).
BITS_Clk is the BITS clock output at either 1.544 MHz or 2.048 MHz. It is selected by the BITS_Sel input and its state
may be read in bit 2 of the Ctl_Mode register. When BITS_Sel = 1, the BITS frequency is 1.544 MHz, and when
BITS_Sel = 0, the BITS frequency is 2.048 MHz This output clock is digital-synthesized from the SYNC_CLK directly,
and will be synchronized to SYNC_8K and SYNC_2K.
Preliminary Data Sheet #: TM061 Page 16 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice